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cypress semiconductor corporation ? 198 champion court ? san jose , ca 95134-1709 ? 408-943-2600 document number: 002-00648 rev. *j revised november 15, 2017 ?spansion, inc.? and ?cypress semiconductor corp.? have merged together to deliver high-performance, high-quality solutions at the heart of today's mo st advanced embedded systems, from automotive, industrial and networ king platforms to highly interactive consumer and mobile devices. the new company ?cypress semiconductor corp.? will continue to offer ?spansion, inc.? products to new and existing customers. continuity of specifications there is no change to this docume nt as a result of offering the device as a cypress product. any changes that have been made are the result of normal document improvements and are noted in the document history page, where supported. future revisions will occur when appropriate, and changes will be noted in a document history page. continuity of orde ring part numbers cypress continues to support existing part numbers. to order these products, please use only the ordering part numbers listed i n this document. for more information please visit our website at www.cypress.com or contact your local sales office for additional information about cypress products and services. our customers cypress is for true innovators ? in companies both large and small. our customers are smart, aggressive, out-of-the-box thinkers wh o design and develop game-changing products that revolutionize their industries or create new indu stries with products and solutions that nobody ever thought of before. about cypress founded in 1982, cypress is the leader in advanced embedded syst em solutions for the world?s most innovative automotive, industrial, home automation and appliances, consumer electronics and medical products. cypress? s programmable systems-on- chip, general-purpose microcontrollers, analog ics, wireless and usb-based connectivity solutions and reliable, high-performanc e memories help engineers design differentiated products and get them to market first. cypress is committed to providing custom ers with the best support and engineering resources on the planet enabling innovators and out-of-the-box thinkers to disrupt markets and create new product categories in record time. to learn more, go to www.cypress.com .
S25FL129P 128-mbit 3.0 v flash memory cypress semiconductor corporation ? 198 champion court ? san jose , ca 95134-1709 ? 408-943-2600 document number: 002-00648 rev. *j revised november 15, 2017 this product is not recommended for new and current designs . for new and current designs, s25fl128s supersedes S25FL129P. this is the factory-recommended migration path. please refer to the s25fl128s dat a sheet for specifications and ordering information. distinctive characteristics architectural advantages ? single power supply operation ? full voltage range: 2.7 to 3.6v read and write operations ? memory architecture ? uniform 64 kb sectors ? top or bottom parameter block (two 64-kb sectors broken down into sixteen 4-kb sub-sectors each) ? uniform 256 kb sectors (no 4-kb sub-sectors) ? 256-byte page size ? backward compatible with the s25fl128p (uniform 256 kb sector) device ? program ? page program (up to 256 bytes) in 1.5 ms (typical) ? program operations are on a page by page basis ? accelerated programming mode via 9v w#/acc pin ? quad page programming ? erase ? bulk erase function ? sector erase (se) command (d8h) for 64 kb and 256 kb sectors ? sub-sector erase (p4e) command (20h) for 4 kb sectors (for uniform 64-kb sector device only) ? sub-sector erase (p8e) command (40h) for 8 kb sectors (for uniform 64-kb sector device only) ? cycling endurance ? 100,000 cycles per sector typical ? data retention ? 20 years typical ? device id ? jedec standard two-byte electronic signature ? res command one-byte electronic signature for backward compatibility ? one time programmable (otp) area for permanent, secure identification; can be programmed and locked at the factory or by the customer ? cfi (common flash interface) compliant: allows host system to identify and accommodate multiple flash devices ? process technology ? manufactured on 0.09 m mirrorbit ? process technology ? package option ? industry standard pinouts ? 16-pin so package (300 mils) ? 8-contact wson package (6 x 8 mm) ? 24-ball bga (6 x 8 mm) package, 5 x 5 pin configuration ? 24-ball bga (6 x 8 mm) package, 6 x 4 pin configuration performance characteristics ? speed ? normal read (serial): 40 mhz clock rate ? fast_read (serial): 104 mhz clock rate (maximum) ? dual i/o fast_read: 80 mhz clock rate or 20 mb/s effective data rate ? quad i/o fast_read: 80 mhz clock rate or 40 mb/s effective data rate ? power saving standby mode ? standby mode 80 a (typical) ? deep power-down mode 3 a (typical) memory protection features ? memory protection ? w#/acc pin works in conjunction wi th status register bits to protect specified memory areas ? status register block protection bits (bp2, bp1, bp0) in status
document number: 002-00648 rev. *j page 3 of 66 S25FL129P general description the S25FL129P is a 3.0 volt (2.7v to 3.6v), single-power-supply flash memory device. the device is offered in two configurations : 256 uniform 64 kb sectors with the two (top or bottom) 64 kb sectors further split up into thirty-t wo 4 kb sub sectors, or 64 uni form 256 kb sectors. the S25FL129P device is backward compat ible with the s25fl128p (uniform 256 kb sector) device. the device accepts data written to si (serial input) and out puts data on so (serial output). the devices are designed to be programmed in-system with th e standard system 3.0-volt v cc supply. the S25FL129P device adds the following high-performance features using 5 new instructions: ? dual output read using both si and so pins as output pins at a clock rate of up to 80 mhz ? quad output read using si, so, w# /acc and hold# pins as output pins at a clock rate of up to 80 mhz ? dual i/o high performance read using both si and so pins as input and output pins at a clock rate of up to 80 mhz ? quad i/o high performance read using si, so, w#/acc and hold# pins as input and output pins at a clock rate of up to 80 mhz ? quad page programming using si, so, w#/acc and hold# pins as i nput pins to program data at a clock rate of up to 80 mhz the memory can be programmed 1 to 256 bytes at a time, usin g the page program command. the device supports sector erase and bulk erase commands. each device requires only a 3.0-volt power supply (2.7v to 3.6v ) for both read and write functi ons. internally generated and regulated voltages are provided for the program operations. this device requires a high voltage supply to the w#/acc pin to ena ble the accelerated programming mode. the S25FL129P device also offers a one-time programmable area (otp) of up to 128-bits (16 bytes) for permanent secure identification and an additional 490 bytes of otp space for other use. this otp ar ea can be programmed or read using the otpp o r otpr instructions.
document number: 002-00648 rev. *j page 4 of 66 S25FL129P contents distinctive characteristics .................................................. 2 general description ............................................................. 3 1. block diagram .............................................................. 5 2. connection diagrams .................................................. 5 3. input/output descriptions ........................................... 7 4. logic symbol ............................................................... 7 5. ordering information ................................................... 8 5.1 valid combinations ........................................................ 8 6. spi modes ..................................................................... 9 7. device operations ..................................................... 10 7.1 byte or page programming.......................................... 10 7.2 quad page programming ............................................ 10 7.3 dual and quad i/o mode ............................................. 10 7.4 sector erase / bulk erase............................................ 10 7.5 monitoring write operatio ns using the status reg- ister .............................................................................. 10 7.6 active power and standby power modes.................... 10 7.7 status register ............................................................ 11 7.8 configuration register ................................................. 11 7.9 data protection modes ................................................ 13 7.10 hold mode (hold#) .................................................... 14 7.11 accelerated programming op eration........................... 14 8. sector address table ................................................ 15 9. command definitions ................................................ 20 9.1 read data bytes (read) ............................................ 22 9.2 read data bytes at higher speed (fast_read) ...... 23 9.3 dual output read mode (dor)................................... 24 9.4 quad output read mode (qor) ................................. 25 9.5 dual i/o high performance read mode (dior)........ 26 9.6 quad i/o high performance read mode (qior) ........ 28 9.7 read identification (rdid) ..... .............. .............. .......... 29 9.8 read-id (read_id)..................................................... 33 9.9 write enable (wren) .................................................. 34 9.10 write disable (wrdi)................................................... 34 9.11 read status register (rdsr) ..................................... 35 9.12 read configuration register (rcr) ............. ............... 36 9.13 write registers (wrr) ................................................ 37 9.14 page program (pp)....................................................... 39 9.15 quad page program (qpp) ........................................ 40 9.16 parameter sector erase (p4e, p8e) (only applica- ble for the uniform 64 kb sect or device)....................... 41 9.17 sector erase (se)......................................................... 42 9.18 bulk erase (be) ............................................................ 43 9.19 deep power-down (dp) ......... ............... .............. ......... 44 9.20 release from deep power-d own (res)....................... 45 9.21 clear status register (clsr)....................................... 46 9.22 otp program (otpp)................................................... 47 9.23 read otp data bytes (otpr) .............. .............. ......... 47 10. otp regions ............................................................... 48 10.1 programming otp address space............................... 48 10.2 reading otp data ... .............. ............... .............. ......... 48 10.3 locking otp regions........... ........................................ 48 11. power-up and power-down ........................................ 51 12. initial delivery state .................................................... 52 13. program acceleration via w#/acc pin ..................... 52 14. electrical specifications ............................................. 54 14.1 absolute maximum ratings .......................................... 54 15. operating ranges ....................................................... 54 16. dc characteristics ...................................................... 55 17. test conditions ........................................................... 56 18. ac characteristics ...................................................... 57 18.1 capacitance ............ .............. ........... ........... ........... ....... 58 19. physical dimensions .................................................. 60 19.1 so3 016 ? 16-pin wide plastic small outline package (300-mil body width) ..................................... 60 19.2 wson 8-contact (6 x 8 mm) no-lead package (wnf008) ..................................................................... 61 19.3 fab024 ? 24-ball ball grid array (6 x 8 mm) package ........................................................................ 62 19.4 fac024 ? 24-ball ball grid array (6 x 8 mm) package ........................................................................ 63 20. revision history .......................................................... 64
document number: 002-00648 rev. *j page 5 of 66 S25FL129P 1. block diagram 2. connection diagrams figure 2.1 16-pin plastic small outline package (so) note dnc = do not connect (reserved for future use) sram ps logic array - l array - r rd data path io x d e c cs# sck si / io0 so / io1 gnd hold# / io3 v cc w# / acc / io2 1 2 3 4 16 15 14 13 hold#/io3 vcc dnc dnc dnc dnc si/io0 sck 5 6 7 8 12 11 10 9 w#/acc/io2 gnd dnc dnc dnc dnc cs# so/io1
document number: 002-00648 rev. *j page 6 of 66 S25FL129P figure 2.2 8-contact wson package (6 x 8 mm) note there is an exposed central pad on the under side of the wson package. this should no t be connected to any voltage or signal lin e on the pcb. connecting the central pad to gnd (v ss ) is possible, provided pcb routing ensures 0m v difference between voltage at the wson gnd (v ss ) lead and the central exposed pad. figure 2.3 6 x 8 mm 24-ball bga package, 5 x 5 pin configuration figure 2.4 6 x 8 mm 24-ball bga package, 6 x 4 pin configuration 1 2 3 4 5 6 7 8 cs# so/io1 hold#/io 3 sck si/io0 gnd wson w #/acc/io2 vcc 3 25 4 1 nc nc nc nc b d e a c gnd sck nc vcc nc nc cs# nc w#/acc/io2 nc si/io0 so/io1 nc hold#/io3 nc nc nc nc nc nc sck nc nc gnd vcc b2 b3 b4 cs# nc w#/acc/io2 c1 c2 c3 c4 so/io1 si/io0 hold#/io3 d1 d2 d3 d4 nc nc nc e1 e2 e3 nc e4 nc nc nc a2 a3 a4 b1 nc nc nc nc f1 f2 f3 nc f4 nc a1
document number: 002-00648 rev. *j page 7 of 66 S25FL129P 3. input/output descriptions 4. logic symbol signal i/o description so/io1 i/o serial data output : transfers data serially out of the device on the falling edge of sck. functions as an i/o pin in dual and quad i/o, and quad page program modes. si/io0 i/o serial data input : transfers data serially into th e device. device latches commands, addresses, and program data on si on the rising edge of sck. functions as an i/o pin in dual and quad i/o mode. sck input serial clock : provides serial interface timing. latches commands, addresses, and data on si on rising edge of sck. triggers output on so after the falling edge of sck. cs# input chip select : places device in active power mode when driven low. deselects device and places so at high impedance wh en high. after power-up, device requires a fallin g edge on cs# before any command is written. device is in standby mode when a program, erase, or write status register operation is not in progress. hold#/io3 i/o hold : pauses any serial communication with the device without desel ecting it. when driven low, so is at high impedance, and all input at si and sck are ignored. requires that cs# also be driven low. functions as an i/o pin in quad i/o mode. w#/acc/io2 i/o write protect : protects the memory area specified by status register bits bp2:bp0. when driven low, prevents any program or erase co mmand from altering the data in the protected memory area. functions as an i/o pin in quad i/o mode. v cc input supply voltage gnd input ground cs# so/io1 w#/acc/io2 gnd si/io0 sck hold#/io3 v cc
document number: 002-00648 rev. *j page 8 of 66 S25FL129P 5. ordering information this product is not recommended for new and current designs. for new and current designs, s25fl128s supersedes S25FL129P. this is the factory-recommended migratio n path. please refer to the s25fl128s dat a sheet for specifications and ordering information. the ordering part number is formed by a valid combination of the following: 5.1 valid combinations table 5.1 lists the valid combinations configurations pl anned to be supported in volume for this device. note 1. package marking omits the leading ?s25? and speed, package and model number. s25fl 129 p 0x m f i 00 1 packing type (note 1) 0 = tray 1 = tube 3 = 13? tape and reel model number (additional ordering options) 31 = 6x4 pin configuration bga package, uniform 256 kb sectors 30 = 6x4 pin configuration bga package, uniform 64 kb sectors 21 = 5x5 pin configuration bga package, uniform 256 kb sectors 20 = 5x5 pin configuration bga package, uniform 64 kb sectors 01 = so/wson package, uniform 256 kb sectors 00 = so/wson package, uniform 64 kb sectors temperature range i = industrial (?40c to + 85c) v = automotive in-cabin (-40*c to + 105*c) package materials f = lead (pb)-free h = low-halogen, lead (pb)-free package type m = 16-pin so package n = 8-contact wson package b = 24-ball bga 6 x 8 mm package, 1.00 mm pitch speed 0x = 104 mhz device technology p = 0.09 m mirrorbit ? process technology density 129= 128 mbit device family s25fl cypress memory 3.0 volt-only, serial peripheral interface (spi) flash memory table 5.1 S25FL129P valid combinations table S25FL129P valid combinations package marking base ordering part number speed option package and temperature model number packing type S25FL129P 0x mfi, nfi mfv , nfv 00 0, 1, 3 fl129p + (temp) + f 01 fl129p + (temp) + fl bhi bhv 20, 30 0, 3 fl129p + (temp) + f 21, 31 fl129p + (temp) + fl
document number: 002-00648 rev. *j page 9 of 66 S25FL129P 6. spi modes a microcontroller can use either of its two spi m odes to control cypress spi flash memory devices: ? cpol = 0, cpha = 0 (mode 0) ? cpol = 1, cpha = 1 (mode 3) input data is latched in on the rising e dge of sck, and output data is available fr om the falling edge of sck for both modes. when the bus master is in stan dby mode, sck is as shown in figure 6.2 for each of the two modes: ? sck remains at 0 for (cpol = 0, cpha = 0 mode 0) ? sck remains at 1 for (cpol = 1, cpha = 1 mode 3) figure 6.1 bus master and memory devices on the spi bus note the write protect/accelerated programming (w#/acc) and hold (hol d#) signals should be driven high (logic level 1) or low (logic level 0) as appropriate. figure 6.2 spi modes supported spi interface with (cpol, cpha) = (0, 0) or (1, 1) bus master cs3 cs2 cs1 spi memory device spi memory device spi memory device cs# hold# cs# hold# cs# hold# sck so si sck so si sck so si so si sck w#/acc w#/acc w#/acc msb msb sck sck si so cpha cpol 00 11 cs# mode 0 mode 3
document number: 002-00648 rev. *j page 10 of 66 S25FL129P 7. device operations all cypress spi devices accept and output data in bytes (8 bits at a time). the spi device is a slave device that supports an i nactive clock while cs# is held low. 7.1 byte or page programming programming data requires two commands: write enable (wren), which is one byte, and a page program (pp) sequence, which consists of four bytes plus data. the page program sequence accept s from 1 byte up to 256 consecut ive bytes of data (which is t he size of one page) to be programmed in one operation. programming means that bits can ei ther be left at 0, or programmed from 1 to 0. changing bits from 0 to 1 requires an erase operation. 7.2 quad page programming the quad page program (qpp) instruction allows up to 256 byte s of data to be programmed using 4 pins as inputs at the same time, thus effectively quadrupling the data transfer rate, compar ed to the page program (pp) in struction. the write enable latc h (wel) bit must be set to a 1 using the write enab le (wren) command prior to issuing the qpp command. 7.3 dual and quad i/o mode the S25FL129P device supports dual and quad i/o operation when using the dual/quad output read mode and the dual/quad i/ o high performance mode instructions. using th e dual or quad i/o instructions allows dat a to be transferred to or from the devi ce at two to four times the rate of standard spi devices. when operati ng in the dual or quad i/o high performance mode (bbh or ebh instructions), data can be read at fast speed using two or four data bits at a time, and the 3-byte address can be input two or four address bits at a time. 7.4 sector erase / bulk erase the sector erase (se) and bulk erase (be) co mmands set all the bits in a sector or the entire memory array to 1. while bits can be individually programmed from 1 to 0, erasin g bits from 0 to 1 must be done on a secto r-wide (se) or array-wide (be) level. in a ddition to the 64-kb sector erase (se), the s25fl12 9p device also offers 4-kb parameter sect or erase (p4e) and 8-kb parameter sector erase (p8e) (only applicable for th e uniform 64 kb sector device). 7.5 monitoring write operations using the status register the host system can determine when a write register, program, or erase operation is complete by monitoring the write in progres s (wip) bit in the status register. the read from status register command provides t he state of the wip bit. in addition, the S25FL129P device offers two additional bits in the status regi ster (p_err, e_err) to indica te whether a program or erase operation was a success or failure. 7.6 active power and standby power modes the device is enabled and in the active power mode when chip se lect (cs#) is low. when cs# is high, the device is disabled, but may still be in the active power mode until all program, erase, and write registers operations have completed. the device then goes into the standby power mode, and power consumption drops to i sb . the deep power-down (dp) command provides additional data protection against inadvertent signals. after wr iting the dp command, the device ignores any further program or erase commands, and reduces its power consumption to i dp .
document number: 002-00648 rev. *j page 11 of 66 S25FL129P 7.7 status register the status register contains the status and control bits that can be read or set by specific commands (see table 9.1 on page 21 ). these bits configure different protection configurations and supply information of operatio n of the device. (for details see table 9.8, S25FL129P status register on page 35 ): ? write in progress (wip): indicates whether the device is performing a write registers, program or erase operation. ? write enable latch (wel): indicates the status of th e internal write enable latch. ? block protect (bp2, bp1, bp0): non-volatile bits that define memory area to be software-protected against program and erase commands. ? erase error (e_err): the erase error bit is used as an er ase operation success and failure check. ? program error (p_err): the program error bit is used as an pr ogram operation success and failure check. ? status register write disable (srwd): places the device in the hardware protected mode when this bit is set to 1 and the w#/acc input is driven low. in this mode, the non-volatile bits of the status register (srwd, bp2, bp1, bp0) become read-only bits. 7.8 configuration register the configuration register contains the cont rol bits that can be read or set by spec ific commands. these bits configure differe nt configurations and security features of the device. ? the freeze bit locks the bp2-0 bits in st atus register and the tbprot and tbparm bits in the conf iguration register. note that once the freeze bit has been set to ?1?, then it ca nnot be cleared to ?0? until a power-on-reset is executed. as long as the freeze bit is set to ?0?, then the other bits of the configuration register, incl uding freeze bit, can be written to. ? the quad bit is non-volatile and sets the pin out of the device to quad mode; that is, w#/acc becomes io2 and hold# becomes io3. the instructions for serial, dual output, and dual i/o reads function as normal. the w#/acc and hold# functionality does not work when the device is set in quad mode. ? the tbparm bit defines the logical location of the 4 kb parame ter sectors. the parameter sect ors consist of thirty two 4 kb sectors. all sectors other than the parameter sectors are def ined to be 64-kb uniform in size. when tbparm is set to a ?1?, the 4 kb parameter sectors starts at the top of the arra y. when tbparm is set to a ?0?, the 4 kb parameter sectors starts at the bottom of the array. note that once this bit is set to a '1', it cannot be changed back to '0'. (this function is not applicable to the uniform 256 kb sector product.) the desir ed state of tbparm must be selected during the initial configuration of the device du ring system manufacture; before the first program or erase operation on the main flash array. tbparm must not be programmed after programming or erasing is done in the main flash array. ? the bpnv bit defines whether or not the bp2-0 bits in the status register are volatile or non-volatile. when bpnv is set to a ?1?, the bp2-0 bits in the status register are volatile and w ill be reset to binary 111 after power on reset. when bpnv is set to a ?0?, the bp2-0 bits in the status register are non-volatile. note that once th is bit is set to a '1', it cannot be cha nged back to '0'. ? the tbprot bit defines the operation of the block protection bits bp2, bp1, and bp0 in the status register. when tbprot is set to a ?0?, then the block pr otection is defined to start from the top of the array. when tbprot is set to a ?1?, then the block protection is defined to start from the bottom of the array. note that on ce this bit is set to a '1', it cannot be changed back to '0'. the desired state of tbprot must be sele cted during the initial configuration of the device during system manufacture; before the first program or erase operation on the main flash array. tbprot must not be programmed after programming or erasing is done in the main flash array.
document number: 002-00648 rev. *j page 12 of 66 S25FL129P note: it is suggested that the block protection and parameter sectors not be set to the same area of the array; otherwise, the user cannot utilize the parameter sectors if they are protected. the following matrix shows the recommended settings. note (default) indicates the value of each configuration register bit set upon initial factory shipment. note 1. (default) indicates the value of each configuration register bit set upon initial factory shipment. tbparm tbprot array overview 00 parameter sectors - bottom bp protection - top (default) 0 1 not recommended (parameters and bp protection are both bottom) 1 0 not recommended (parameters and bp protection are both top) 11 parameter sectors - top of array (high address) bp protection - bottom of array (low address) table 7.1 configuration register table (uniform 64 kb sector) bit bit name bit function description 7na- not used 6na- not used 5 tbprot configures start of block protection 1 = bottom array (low address) 0 = top array (high address) (default) 4 na - do not use 3 bpnv configures bp2-0 bits in the status register 1 = volatile 0 = non-volatile (default) 2 tbparm configures parameter sector location 1 = top array (high address) 0 = bottom array (low address) (default) 1 quad puts the device into quad i/o mode 1 = quad i/o 0 = dual or serial i/o (default) 0 freeze locks bp2-0 bits in the status register 1 = enabled 0 = disabled (default) table 7.2 configuration register table (uniform 256 kb sector) bit bit name bit function description 7 n/a - not used 6 n/a - not used 5 tbprot configures start of block protection 1 = bottom array (low address) 0 = top array (high address) (default) 4 n/a - do not use 3 bpnv configures bp2-0 bits in the status register 1 = volatile 0 = non-volatile (default) 2 n/a - do not use 1 quad puts the device into quad i/o mode 1 = quad i/o 0 = dual or serial i/o (default) 0 freeze locks bp2-0 bits in the status register 1 = enabled 0 = disabled (default)
document number: 002-00648 rev. *j page 13 of 66 S25FL129P 7.9 data protection modes cypress spi flash memory devices provi de the following data protection methods: ? the write enable (wren) command: must be written prior to any command that modifies data. the wren command sets the write enable latch (wel) bit. the wel bit resets (disables writes) on power-up or after the device completes the following commands: ? page program (pp) ? sector erase (se) ? bulk erase (be) ? write disable (wrdi) ? write register (wrr) ? parameter 4 kb sector erase (p4e) ? parameter 8 kb sector erase (p8e) ? quad page programming (qpp) ? otp byte programming (otpp) ? software protected mode (spm): the block protect bp2, bp1, bp0 bits define the section of the me mory array that can be read but not programmed or erased. table 7.3 and table 7.4 shows the sizes and address ranges of protected areas that are defined by status register bits bp2:bp0. ? hardware protected mode (hpm): the write protect (w#/acc) input and the st atus register write disable (srwd) bit together provide write protection. ? clock pulse count: the device verifies that all program, erase, and wr ite register commands consist of a clock pulse count that is a multiple of eight before executing them. table 7.3 tbprot = 0 (starts protection from top of array) status register block memory array protected portion of total memory area bp2 bp1 bp0 protected address range protected sectors unprotected address range unprotected sectors uniform 64 kb uniform 256 kb uniform 64 kb uniform 256 kb 0 0 0 none 0 0 000000h - ffffffh sa255:sa0 sa63:sa0 0 0 0 1 fc0000h - ffffffh (4) sa255:sa252 (1) sa63 000000h - fbffffh sa251:sa0 sa62:sa0 1/64 0 1 0 f80000h - ffffffh (8) sa255:sa248 (2)sa 63:sa62 000000h - f7ffff h sa247:sa0 sa61:sa0 1/32 0 1 1 f00000h - ffffffh (16) sa255:sa240 (4)sa 63:sa60 000000h - eff fffh sa239:sa0 sa59:sa0 1/16 1 0 0 e00000h - ffffffh (32) sa255:sa224 (8)s a63:sa56 000000h - dfffffh sa223:sa0 sa55:sa0 1/8 1 0 1 c00000h - ffffffh (64)sa255:sa192 (16)sa63: sa48 000000h - bfffffh sa191:sa0 sa47:sa0 1/4 1 1 0 800000h - ffffffh (128)sa255:sa128 (32)sa63: sa32 000000h - 7fffffh sa127:sa0 sa31:sa0 1/2 1 1 1 000000h - ffffffh (256)sa255:sa0 (64)sa63:sa0 none none none all table 7.4 tbprot = 1 (starts protection from bottom of array) status register block memory array protected portion of total memory area bp2 bp1 bp0 protected address range protected sectors unprotected address range unprotected sectors uniform 64 kb uniform 256 kb uniform 64 kb uniform 256 kb 0 0 0 none 0 0 000000h - ffffffh sa0:sa255 sa0:sa63 0 0 0 1 000000h - 03ffffh (4) sa0:sa3 (1) sa0 040000h - ffffffh sa4:sa255 sa1:sa63 1/64 0 1 0 000000h - 07ffffh (8) sa0:sa7 (2)sa0:sa1 080000h - ffffffh sa8:sa255 sa2:sa63 1/32 0 1 1 000000h - 0fffffh (16)sa0:sa15 (4)sa0: sa3 100000h - ffffffh sa16:sa255 sa4:sa63 1/16 1 0 0 000000h - 1fffffh (32)sa0:sa31 (8)sa 0:sa7 200000h - ffffffh sa32:sa255 sa8:sa63 1/8
document number: 002-00648 rev. *j page 14 of 66 S25FL129P 7.10 hold mode (hold#) the hold input (hold#) stops any serial communication with the dev ice, but does not terminate any write registers, program or erase operation that is currently in progress. the hold mode starts on the falling edge of hold# if sck is also low (see figure 7.1 , standard use). if the falling edge of hold# does not occur while sck is low, the hold mode begins after the next falling edge of sck (non-standard use). the hold mode ends on the rising edge of ho ld# signal (standard use) if sck is also low. if the rising edge of hold# does not occur while sck is low, the hold mode ends on th e next falling edge of clk (non-standard use) see figure 7.1 . the so output is high impedance, and the si and sck inputs are ignored (don?t care) for the duration of the hold mode. cs# must remain low for the entire duration of the hold mode to ensure that the device internal logic remains unchanged. if cs# goes high while the device is in the hold mode, the internal logi c is reset. to prevent the device from reverting to the hold m ode when device communication is resumed, hold# mu st be held high, followed by driving cs# low. note: the hold mode feature is disabled during quad i/o mode. figure 7.1 hold mode operation 7.11 accelerated programming operation the device offers accelerated program operat ions through the acc function. this functi on is primarily intended to allow faster manufacturing throughput at the fa ctory. if the system asserts v hh on this pin, the device uses the higher voltage on the pin to reduce the time required for program operations. removing v hh from the w#/acc pin returns the device to normal operation. note that the w#/acc pin must not be at v hh for operations other than accelerated programming, or device damage may result. in addition, the w#/acc pin must not be left floating or unco nnected; inconsistent behavior of the device may result. note: the acc function is disabled during quad i/o mode. 1 0 1 000000h - 3fffffh (64)sa0:sa63 (16)sa0: sa15 400000h - ffffffh sa64:sa255 sa16:sa63 1/4 1 1 0 000000h - 7fffffh (128)sa0:sa127 (32)sa 0:sa31 800000h - ffffffh sa128:255 sa32:sa63 1/2 1 1 1 000000h - ffffffh (256)sa0:sa255 (64)sa0:sa63 none none none all table 7.4 tbprot = 1 (starts protection from bottom of array) status register block memory array protected portion of total memory area bp2 bp1 bp0 protected address range protected sectors unprotected address range unprotected sectors uniform 64 kb uniform 256 kb uniform 64 kb uniform 256 kb sck hold# hold condition (standard use) hold condition (non-standard use)
document number: 002-00648 rev. *j page 15 of 66 S25FL129P 8. sector address table the sector address tables show the size of the memory array, sectors, and pages. th e device uses pages to cache the program data before the data is programmed into the memory array. ea ch page or byte can be individually programmed (bits are changed from 1 to 0). the data is erased (bits are changed from 0 to 1) on a sub-sector, sector- or device-wide basis using the p4e/p8e (applicable only for the uniform 64 kb sector device), se or be commands. table 8.1 to table 8.3 show the starting and ending address for each sector. th e complete set of sectors comprises th e memory array of the flash device. table 8.1 S25FL129P sector address table (uniform 256 kb sector) sector address range sector address range start address end address start address end address 63 fc0000h ffffffh 31 7c0000h 7fffffh 62 f80000h fbffffh 30 780000h 7bffffh 61 f40000h f7ffffh 29 740000h 77ffffh 60 f00000h f3ffffh 28 700000h 73ffffh 59 ec0000h efffffh 27 6c0000h 6fffffh 58 e80000h ebffffh 26 680000h 6bffffh 57 e40000h e7ffffh 25 640000h 67ffffh 56 e00000h e3ffffh 24 600000h 63ffffh 55 dc0000h dfffffh 23 5c0000h 5fffffh 54 d80000h dbffffh 22 580000h 5bffffh 53 d40000h d7ffffh 21 540000h 57ffffh 52 d00000h d3ffffh 20 500000h 53ffffh 51 cc0000h cfffffh 19 4c0000h 4fffffh 50 c80000h cbffffh 18 480000h 4bffffh 49 c40000h c7ffffh 17 440000h 47ffffh 48 c00000h c3ffffh 16 400000h 43ffffh 47 bc0000h bfffffh 15 3c0000h 3fffffh 46 b80000h bbffffh 14 380000h 3bffffh 45 b40000h b7ffffh 13 340000h 37ffffh 44 b00000h b3ffffh 12 300000h 33ffffh 43 ac0000h afffffh 11 2c0000h 2fffffh 42 a80000h abffffh 10 280000h 2bffffh 41 a40000h a7ffffh 9 240000h 27ffffh 40 a00000h a3ffffh 8 200000h 23ffffh 39 9c0000h 9fffffh 7 1c0000h 1fffffh 38 980000h 9bffffh 6 180000h 1bffffh 37 940000h 97ffffh 5 140000h 17ffffh 36 900000h 93ffffh 4 100000h 13ffffh 35 8c0000h 8fffffh 3 0c0000h 0fffffh 34 880000h 8bffffh 2 080000h 0bffffh 33 840000h 87ffffh 1 040000h 07ffffh 32 800000h 83ffffh 0 000000h 03ffffh
document number: 002-00648 rev. *j page 16 of 66 S25FL129P table 8.2 S25FL129P sector address table (uniform 64 kb sector, tbparm=0) (sheet 1 of 2) sector address range sector address range sector address range start address end address start addres s end address start address end address sa108 6c0000h 6cffffh sa61 3d0000h 3dffffh sa14 0e0000h 0effffh sa107 6b0000h 6bffffh sa60 3c0000h 3cffffh sa13 0d0000h 0dffffh sa106 6a0000h 6affffh sa59 3b0000h 3bffffh sa12 0c0000h 0cffffh sa105 690000h 69ffffh sa58 3a0000h 3affffh sa11 0b0000h 0bffffh sa104 680000h 68ffffh sa57 390000h 39ffffh sa10 0a0000h 0affffh sa103 670000h 67ffffh sa56 380000h 38ffffh sa9 090000h 09ffffh sa102 660000h 66ffffh sa55 370000h 37ffffh sa8 080000h 08ffffh sa101 650000h 65ffffh sa54 360000h 36ffffh sa7 070000h 07ffffh sa100 640000h 64ffffh sa53 350000h 35ffffh sa6 060000h 06ffffh sa99 630000h 63ffffh sa52 340000h 34ffffh sa5 050000h 05ffffh sa98 620000h 62ffffh sa51 330000h 33ffffh sa4 040000h 04ffffh sa97 610000h 61ffffh sa50 320000h 32ffffh sa3 030000h 03ffffh sa96 600000h 60ffffh sa49 310000h 31ffffh sa2 020000h 02ffffh sa95 5f0000h 5fffffh sa48 300000h 30ffffh sa1 010000h 01ffffh sa94 5e0000h 5effffh sa47 2f0000h 2fffffh sa0 000000h 00ffffh sa93 5d0000h 5dffffh sa46 2e0000h 2effffh ss31 01f000h 01ffffh sa92 5c0000h 5cffffh sa45 2d0000h 2dffffh ss30 01e000h 01efffh sa91 5b0000h 5bffffh sa44 2c0000h 2cffffh ss29 01d000h 01dfffh sa90 5a0000h 5affffh sa43 2b0000h 2bffffh ss28 01c000h 01cfffh sa89 590000h 59ffffh sa42 2a0000h 2affffh ss27 01b000h 01bfffh sa88 580000h 58ffffh sa41 290000h 29ffffh ss26 01a000h 01afffh sa87 570000h 57ffffh sa40 280000h 28ffffh ss25 019000h 019fffh sa86 560000h 56ffffh sa39 270000h 27ffffh ss24 018000h 018fffh sa85 550000h 55ffffh sa38 260000h 26ffffh ss23 017000h 017fffh sa84 540000h 54ffffh sa37 250000h 25ffffh ss22 016000h 016fffh sa83 530000h 53ffffh sa36 240000h 24ffffh ss21 015000h 015fffh sa82 520000h 52ffffh sa35 230000h 23ffffh ss20 014000h 014fffh sa81 510000h 51ffffh sa34 220000h 22ffffh ss19 013000h 013fffh sa80 500000h 50ffffh sa33 210000h 21ffffh ss18 012000h 012fffh sa79 4f0000h 4fffffh sa32 200000h 20ffffh ss17 011000h 011fffh sa78 4e0000h 4effffh sa31 1f0000h 1fffffh ss16 010000h 010fffh sa77 4d0000h 4dffffh sa30 1e0000h 1effffh ss15 00f000h 00ffffh sa76 4c0000h 4cffffh sa29 1d0000h 1dffffh ss14 00e000h 00efffh sa75 4b0000h 4bffffh sa28 1c0000h 1cffffh ss13 00d000h 00dfffh sa74 4a0000h 4affffh sa27 1b0000h 1bffffh ss12 00c000h 00cfffh sa73 490000h 49ffffh sa26 1a0000h 1affffh ss11 00b000h 00bfffh sa72 480000h 48ffffh sa25 190000h 19ffffh ss10 00a000h 00afffh sa71 470000h 47ffffh sa24 180000h 18ffffh ss9 009000h 009fffh sa70 460000h 46ffffh sa23 170000h 17ffffh ss8 008000h 008fffh sa69 450000h 45ffffh sa22 160000h 16ffffh ss7 007000h 007fffh sa68 440000h 44ffffh sa21 150000h 15ffffh ss6 006000h 006fffh sa67 430000h 43ffffh sa20 140000h 14ffffh ss5 005000h 005fffh sa66 420000h 42ffffh sa19 130000h 13ffffh ss4 004000h 004fffh sa65 410000h 41ffffh sa18 120000h 12ffffh ss3 003000h 003fffh sa64 400000h 40ffffh sa17 110000h 11ffffh ss2 002000h 002fffh sa63 3f0000h 3fffffh sa16 100000h 10ffffh ss1 001000h 001fffh sa62 3e0000h 3effffh sa15 0f0000h 0fffffh ss0 000000h 000fffh
document number: 002-00648 rev. *j page 17 of 66 S25FL129P note sector sa0 is split up into sub-se ctors ss0 - ss15 (dark gray shading) sector sa1 is split up into sub-se ctors ss16 - ss31(light gray shading) sa255 ff0000h ffffffh sa206 ce0000h ceffffh sa157 9d0000h 9dffffh sa254 fe0000h feffffh sa205 cd0000h cdffffh sa156 9c0000h 9cffffh sa253 fd0000h fdffffh sa204 cc0000h ccffffh sa155 9b0000h 9bffffh sa252 fc0000h fcffffh sa203 cb0000h cbffffh sa154 9a0000h 9affffh sa251 fb0000h fbffffh sa202 ca0000h caffffh sa153 990000h 99ffffh sa250 fa0000h faffffh sa201 c90000h c9ffffh sa152 980000h 98ffffh sa249 f90000h f9ffffh sa200 c80000h c8ffffh sa151 970000h 97ffffh sa248 f80000h f8ffffh sa199 c70000h c7ffffh sa150 960000h 96ffffh sa247 f70000h f7ffffh sa198 c60000h c6ffffh sa149 950000h 95ffffh sa246 f60000h f6ffffh sa197 c50000h c5ffffh sa148 940000h 94ffffh sa245 f50000h f5ffffh sa196 c40000h c4ffffh sa147 930000h 93ffffh sa244 f40000h f4ffffh sa195 c30000h c3ffffh sa146 920000h 92ffffh sa243 f30000h f3ffffh sa194 c20000h c2ffffh sa145 910000h 91ffffh sa242 f20000h f2ffffh sa193 c10000h c1ffffh sa144 900000h 90ffffh sa241 f10000h f1ffffh sa192 c00000h c0ffffh sa143 8f0000h 8fffffh sa240 f00000h f0ffffh sa191 bf0000h bfffffh sa142 8e0000h 8effffh sa239 ef0000h efffffh sa190 be0000h beffffh sa141 8d0000h 8dffffh sa238 ee0000h eeffffh sa189 bd0000h bdffffh sa140 8c0000h 8cffffh sa237 ed0000h edffffh sa188 bc0000h bcffffh sa139 8b0000h 8bffffh sa236 ec0000h ecffffh sa187 bb0000h bbffffh sa138 8a0000h 8affffh sa235 eb0000h ebffffh sa186 ba0000h baffffh sa137 890000h 89ffffh sa234 ea0000h eaffffh sa185 b90000h b9ffffh sa136 880000h 88ffffh sa233 e90000h e9ffffh sa184 b80000h b8ffffh sa135 870000h 87ffffh sa232 e80000h e8ffffh sa183 b70000h b7ffffh sa134 860000h 86ffffh sa231 e70000h e7ffffh sa182 b60000h b6ffffh sa133 850000h 85ffffh sa230 e60000h e6ffffh sa181 b50000h b5ffffh sa132 840000h 84ffffh sa229 e50000h e5ffffh sa180 b40000h b4ffffh sa131 830000h 83ffffh sa228 e40000h e4ffffh sa179 b30000h b3ffffh sa130 820000h 82ffffh sa227 e30000h e3ffffh sa178 b20000h b2ffffh sa129 810000h 81ffffh sa226 e20000h e2ffffh sa177 b10000h b1ffffh sa128 800000h 80ffffh sa225 e10000h e1ffffh sa176 b00000h b0ffffh sa127 7f0000h 7fffffh sa224 e00000h e0ffffh sa175 af0000h afffffh sa126 7e0000h 7effffh sa223 df0000h dfffffh sa174 ae0000h aeffffh sa125 7d0000h 7dffffh sa222 de0000h deffffh sa173 ad0000h adffffh sa124 7c0000h 7cffffh sa221 dd0000h ddffffh sa172 ac0000h acffffh sa123 7b0000h 7bffffh sa220 dc0000h dcffffh sa171 ab0000h abffffh sa122 7a0000h 7affffh sa219 db0000h dbffffh sa170 aa0000h aaffffh sa121 790000h 79ffffh sa218 da0000h daffffh sa169 a90000h a9ffffh sa120 780000h 78ffffh sa217 d90000h d9ffffh sa168 a80000h a8ffffh sa119 770000h 77ffffh sa216 d80000h d8ffffh sa167 a70000h a7ffffh sa118 760000h 76ffffh sa215 d70000h d7ffffh sa166 a60000h a6ffffh sa117 750000h 75ffffh sa214 d60000h d6ffffh sa165 a50000h a5ffffh sa116 740000h 74ffffh sa213 d50000h d5ffffh sa164 a40000h a4ffffh sa115 730000h 73ffffh sa212 d40000h d4ffffh sa163 a30000h a3ffffh sa114 720000h 72ffffh sa211 d30000h d3ffffh sa162 a20000h a2ffffh sa113 710000h 71ffffh sa210 d20000h d2ffffh sa161 a10000h a1ffffh sa112 700000h 70ffffh sa209 d10000h d1ffffh sa160 a00000h a0ffffh sa111 6f0000h 6fffffh sa208 d00000h d0ffffh sa159 9f0000h 9fffffh sa110 6e0000h 6effffh sa207 cf0000h cfffffh sa158 9e0000h 9effffh sa109 6d0000h 6dffffh table 8.2 S25FL129P sector address table (uniform 64 kb sector, tbparm=0) (sheet 2 of 2) sector address range sector address range sector address range start address end address start addres s end address start address end address
document number: 002-00648 rev. *j page 18 of 66 S25FL129P table 8.3 S25FL129P sector address table (uniform 64 kb sector, tbparm=1) (sheet 1 of 2) sector address range sector address range sector address range start address end address start addres s end address start address end address ss31 fff000h ffffffh sa239 ef0000h efffffh sa191 bf0000h bfffffh ss30 ffe000h ffefffh sa238 ee0000h eeffffh sa190 be0000h beffffh ss29 ffd000h ffdfffh sa237 ed0000h edffffh sa189 bd0000h bdffffh ss28 ffc000h ffcfffh sa236 ec0000h ecffffh sa188 bc0000h bcffffh ss27 ffb000h ffbfffh sa235 eb0000h ebffffh sa187 bb0000h bbffffh ss26 ffa000h ffafffh sa234 ea0000h eaffffh sa186 ba0000h baffffh ss25 ff9000h ff9fffh sa233 e90000h e9ffffh sa185 b90000h b9ffffh ss24 ff8000h ff8fffh sa232 e80000h e8ffffh sa184 b80000h b8ffffh ss23 ff7000h ff7fffh sa231 e70000h e7ffffh sa183 b70000h b7ffffh ss22 ff6000h ff6fffh sa230 e60000h e6ffffh sa182 b60000h b6ffffh ss21 ff5000h ff5fffh sa229 e50000h e5ffffh sa181 b50000h b5ffffh ss20 ff4000h ff4fffh sa228 e40000h e4ffffh sa180 b40000h b4ffffh ss19 ff3000h ff3fffh sa227 e30000h e3ffffh sa179 b30000h b3ffffh ss18 ff2000h ff2fffh sa226 e20000h e2ffffh sa178 b20000h b2ffffh ss17 ff1000h ff1fffh sa225 e10000h e1ffffh sa177 b10000h b1ffffh ss16 ff0000h ff0fffh sa224 e00000h e0ffffh sa176 b00000h b0ffffh ss15 fef000h feffffh sa223 df0000h dfffffh sa175 af0000h afffffh ss14 fee000h feefffh sa222 de0000h deffffh sa174 ae0000h aeffffh ss13 fed000h fedfffh sa221 dd0000h ddffffh sa173 ad0000h adffffh ss12 fec000h fecfffh sa220 dc0000h dcffffh sa172 ac0000h acffffh ss11 feb000h febfffh sa219 db0000h dbffffh sa171 ab0000h abffffh ss10 fea000h feafffh sa218 da0000h daffffh sa170 aa0000h aaffffh ss9 fe9000h fe9fffh sa217 d90000h d9ffffh sa169 a90000h a9ffffh ss8 fe8000h fe8fffh sa216 d80000h d8ffffh sa168 a80000h a8ffffh ss7 fe7000h fe7fffh sa215 d70000h d7ffffh sa167 a70000h a7ffffh ss6 fe6000h fe6fffh sa214 d60000h d6ffffh sa166 a60000h a6ffffh ss5 fe5000h fe5fffh sa213 d50000h d5ffffh sa165 a50000h a5ffffh ss4 fe4000h fe4fffh sa212 d40000h d4ffffh sa164 a40000h a4ffffh ss3 fe3000h fe3fffh sa211 d30000h d3ffffh sa163 a30000h a3ffffh ss2 fe2000h fe2fffh sa210 d20000h d2ffffh sa162 a20000h a2ffffh ss1 fe1000h fe1fffh sa209 d10000h d1ffffh sa161 a10000h a1ffffh ss0 fe0000h fe0fffh sa208 d00000h d0ffffh sa160 a00000h a0ffffh sa255 ff0000h ffffffh sa207 cf0000h cfffffh sa159 9f0000h 9fffffh sa254 fe0000h feffffh sa206 ce0000h ceffffh sa158 9e0000h 9effffh sa253 fd0000h fdffffh sa205 cd0000h cdffffh sa157 9d0000h 9dffffh sa252 fc0000h fcffffh sa204 cc0000h ccffffh sa156 9c0000h 9cffffh sa251 fb0000h fbffffh sa203 cb0000h cbffffh sa155 9b0000h 9bffffh sa250 fa0000h faffffh sa202 ca0000h caffffh sa154 9a0000h 9affffh sa249 f90000h f9ffffh sa201 c90000h c9ffffh sa153 990000h 99ffffh sa248 f80000h f8ffffh sa200 c80000h c8ffffh sa152 980000h 98ffffh sa247 f70000h f7ffffh sa199 c70000h c7ffffh sa151 970000h 97ffffh sa246 f60000h f6ffffh sa198 c60000h c6ffffh sa150 960000h 96ffffh sa245 f50000h f5ffffh sa197 c50000h c5ffffh sa149 950000h 95ffffh sa244 f40000h f4ffffh sa196 c40000h c4ffffh sa148 940000h 94ffffh sa243 f30000h f3ffffh sa195 c30000h c3ffffh sa147 930000h 93ffffh sa242 f20000h f2ffffh sa194 c20000h c2ffffh sa146 920000h 92ffffh sa241 f10000h f1ffffh sa193 c10000h c1ffffh sa145 910000h 91ffffh sa240 f00000h f0ffffh sa192 c00000h c0ffffh sa144 900000h 90ffffh
document number: 002-00648 rev. *j page 19 of 66 S25FL129P note sector sa254 is split up into sub-sectors ss0 - ss15 (dark gray shading) sector sa255 is split up into sub-sectors ss16 - ss31(light gray shading) sa143 8f0000h 8fffffh sa95 5f0000h 5fffffh sa47 2f0000h 2fffffh sa142 8e0000h 8effffh sa94 5e0000h 5effffh sa46 2e0000h 2effffh sa141 8d0000h 8dffffh sa93 5d0000h 5dffffh sa45 2d0000h 2dffffh sa140 8c0000h 8cffffh sa92 5c0000h 5cffffh sa44 2c0000h 2cffffh sa139 8b0000h 8bffffh sa91 5b0000h 5bffffh sa43 2b0000h 2bffffh sa138 8a0000h 8affffh sa90 5a0000h 5affffh sa42 2a0000h 2affffh sa137 890000h 89ffffh sa89 590000h 59ffffh sa41 290000h 29ffffh sa136 880000h 88ffffh sa88 580000h 58ffffh sa40 280000h 28ffffh sa135 870000h 87ffffh sa87 570000h 57ffffh sa39 270000h 27ffffh sa134 860000h 86ffffh sa86 560000h 56ffffh sa38 260000h 26ffffh sa133 850000h 85ffffh sa85 550000h 55ffffh sa37 250000h 25ffffh sa132 840000h 84ffffh sa84 540000h 54ffffh sa36 240000h 24ffffh sa131 830000h 83ffffh sa83 530000h 53ffffh sa35 230000h 23ffffh sa130 820000h 82ffffh sa82 520000h 52ffffh sa34 220000h 22ffffh sa129 810000h 81ffffh sa81 510000h 51ffffh sa33 210000h 21ffffh sa128 800000h 80ffffh sa80 500000h 50ffffh sa32 200000h 20ffffh sa127 7f0000h 7fffffh sa79 4f0000h 4fffffh sa31 1f0000h 1fffffh sa126 7e0000h 7effffh sa78 4e0000h 4effffh sa30 1e0000h 1effffh sa125 7d0000h 7dffffh sa77 4d0000h 4dffffh sa29 1d0000h 1dffffh sa124 7c0000h 7cffffh sa76 4c0000h 4cffffh sa28 1c0000h 1cffffh sa123 7b0000h 7bffffh sa75 4b0000h 4bffffh sa27 1b0000h 1bffffh sa122 7a0000h 7affffh sa74 4a0000h 4affffh sa26 1a0000h 1affffh sa121 790000h 79ffffh sa73 490000h 49ffffh sa25 190000h 19ffffh sa120 780000h 78ffffh sa72 480000h 48ffffh sa24 180000h 18ffffh sa119 770000h 77ffffh sa71 470000h 47ffffh sa23 170000h 17ffffh sa118 760000h 76ffffh sa70 460000h 46ffffh sa22 160000h 16ffffh sa117 750000h 75ffffh sa69 450000h 45ffffh sa21 150000h 15ffffh sa116 740000h 74ffffh sa68 440000h 44ffffh sa20 140000h 14ffffh sa115 730000h 73ffffh sa67 430000h 43ffffh sa19 130000h 13ffffh sa114 720000h 72ffffh sa66 420000h 42ffffh sa18 120000h 12ffffh sa113 710000h 71ffffh sa65 410000h 41ffffh sa17 110000h 11ffffh sa112 700000h 70ffffh sa64 400000h 40ffffh sa16 100000h 10ffffh sa111 6f0000h 6fffffh sa63 3f0000h 3fffffh sa15 0f0000h 0fffffh sa110 6e0000h 6effffh sa62 3e0000h 3effffh sa14 0e0000h 0effffh sa109 6d0000h 6dffffh sa61 3d0000h 3dffffh sa13 0d0000h 0dffffh sa108 6c0000h 6cffffh sa60 3c0000h 3cffffh sa12 0c0000h 0cffffh sa107 6b0000h 6bffffh sa59 3b0000h 3bffffh sa11 0b0000h 0bffffh sa106 6a0000h 6affffh sa58 3a0000h 3affffh sa10 0a0000h 0affffh sa105 690000h 69ffffh sa57 390000h 39ffffh sa9 090000h 09ffffh sa104 680000h 68ffffh sa56 380000h 38ffffh sa8 080000h 08ffffh sa103 670000h 67ffffh sa55 370000h 37ffffh sa7 070000h 07ffffh sa102 660000h 66ffffh sa54 360000h 36ffffh sa6 060000h 06ffffh sa101 650000h 65ffffh sa53 350000h 35ffffh sa5 050000h 05ffffh sa100 640000h 64ffffh sa52 340000h 34ffffh sa4 040000h 04ffffh sa99 630000h 63ffffh sa51 330000h 33ffffh sa3 030000h 03ffffh sa98 620000h 62ffffh sa50 320000h 32ffffh sa2 020000h 02ffffh sa97 610000h 61ffffh sa49 310000h 31ffffh sa1 010000h 01ffffh sa96 600000h 60ffffh sa48 300000h 30ffffh sa0 000000h 00ffffh table 8.3 S25FL129P sector address table (uniform 64 kb sector, tbparm=1) (sheet 2 of 2) sector address range sector address range sector address range start address end address start addres s end address start address end address
document number: 002-00648 rev. *j page 20 of 66 S25FL129P 9. command definitions the host system must shift all commands, addresses, and data in and out of the device, beginni ng with the most significant bit. on the first rising edge of sck after cs# is driven low, the device accepts the one-byte command on si (all commands are one byte long), most significant bit first. each successi ve bit is latched on the rising edge of sck. table 9.1 lists the complete set of commands. every command sequence begins with a one-byte command code . the command may be followed by address, data, both, or nothing, depending on the command. cs# must be driven high af ter the last bit of the command sequence has been written. the read data bytes (read), read data bytes at higher speed (fast_read), dual output read (dor), quad output read (qor), dual i/o high performance read (dior), quad i/o high performance read (qior), read status register (rdsr), read configuration register (rcr), read otp data (otpr), read manuf acturer and device id (read_id), read identification (rdid) and release from deep power-down and read electronic signat ure (res) command sequences are followed by a data output sequence on so. cs# can be driven high after any bit of the sequence is output to terminate the operation. the page program (pp), quad page progr am (qpp), 64 kb sector erase (se), 4 kb parameter sector erase (p4e), 8 kb parameter sector erase (p8e), bulk eras e (be), write status and configuration re gisters (wrr), program otp space (otpp), write enable (wren), or write disable (wrdi) commands requir e that cs# be driven high at a byte boundary, otherwise the command is not executed. since a byte is composed of eight bits , cs# must therefore be driven high when the number of clock pulses after cs# is driven low is an exact multiple of eight. the device ignores any attempt to access the memory array during a write registers, program, or erase operation, and continues the operation uninterrupted. the instruction set is listed in table 9.1 .
document number: 002-00648 rev. *j page 21 of 66 S25FL129P note 1. for uniform 64 kb sector device only. table 9.1 instruction set operation command one byte command code description address byte cycle mode bit cycle dummy byte cycle data byte cycle read read (03h) 0000 0011 read data bytes 3 0 0 1 to ? fast_read (0bh) 0000 1011 read data bytes at fast speed 3 0 1 1 to ? dor (3bh) 0011 1011 dual output read 3 0 1 1 to ? qor (6bh) 0110 1011 quad output read 3 0 1 1 to ? dior (bbh) 1011 1011 dual i/o high performance read 3 1 0 1 to ? qior (ebh) 1110 1011 quad i/o high performance read 3 1 2 1 to ? rdid (9fh) 1001 1111 read identification 0 0 0 1 to 81 read_id (90h) 1001 0000 read manufacturer and device identification 3 0 0 1 to ? write control wren (06h) 0000 0110 write enable 0 0 0 0 wrdi (04h) 0000 0100 write disable 0 0 0 0 erase p4e (1) (20h) 0010 0000 4 kb parameter sector erase 3 0 0 0 p8e (1) (40h) 0100 0000 8 kb (two 4kb) parameter sector erase 3 0 0 0 se (d8h) 1101 1000 64 kb and 256 kb sector erase 3 0 0 0 be (60h) 0110 0000 or (c7h) 1100 0111 bulk erase 0 0 0 0 program pp (02h) 0000 0010 page programming 3 0 0 1 to 256 qpp (32h) 0011 0010 quad page programming 3 0 0 1 to 256 status and configuration register rdsr (05h) 0000 0101 read status register 0 0 0 1 to ? wrr (01h) 0000 0001 write (status and configuration) register 0 0 0 1 to 2 rcr (35h) 0011 0101 read configuration register (cfg) 0 0 0 1 to ? clsr (30h) 0011 0000 reset the erase and program fall flag (srs and sr6) and restore normal operation) 0000 power saving dp (b9h) 1011 1001 deep power-down 0 0 0 0 res (abh) 1010 1011 release from deep power-down mode 0 0 0 0 (abh) 1010 1011 release from deep power-down and read electronic signature 0 0 3 1 to ? otp otpp (42h) 0100 0010 program one byte of data in otp memory space 3 0 0 1 otpr (4bh) 0100 1011 read data in the otp memory space 3 0 1 1 to ?
document number: 002-00648 rev. *j page 22 of 66 S25FL129P 9.1 read data bytes (read) the read data bytes (read) command reads data from the memory array at the frequency (f r ) presented at the sck input, with a maximum speed of 40 mhz. t he host system must first select the device by driv ing cs# low. the read command is then written to si, followed by a 3 byte address (a23-a0). each bit is latched on the rising edge of sck. the memory array data, at that address , are output serially on so at a frequency f r , on the falling edge of sck. figure 9.1 and table 9.1 on page 21 detail the read command sequence. the first add ress byte specified can start at any location of the memory array. the device automatically increments to th e next higher address after each byte of data is output. the enti re memory array can therefore be read with a single read command . when the highest address is reached, the ad dress counter reverts to 00000h, allowing the read sequence to continue indefinitely. the read command is terminated by driving cs# high at any ti me during data output. the device rejects any read command issued while it is executing a program, erase, or write register s operation, and continues t he operation uninterrupted. figure 9.1 read data bytes (read) command sequence command 24 bit address hi-z msb msb data out 1 data out 2 0 31 32 33 34 35 36 37 38 39 30 29 28 10 9 8 7 6 5 4 3 2 1 7 6 5 23 22 21 4 3 2 1 0 3 2 10 7 so si sck cs# mode 3 mode 0
document number: 002-00648 rev. *j page 23 of 66 S25FL129P 9.2 read data bytes at higher speed (fast_read) the fast_read command reads data from the memory array at the frequency (f c ) presented at the sck input, with a maximum speed of 104 mhz. the host system must first select the device by driving cs# low. the fast_read command is then written to si, followed by a 3 byte address (a23-a0) and a dummy byte. each bi t is latched on the rising edge of sck. the memory array data , at that address, are output se rially on so at a frequency f c , on the falling edge of sck. the fast_read command sequence is shown in figure 9.2 and table 9.1 on page 21 . the first address byte specified can start at any location of the memory array. the devi ce automatically increments to the next higher address after each byte of data is out put. the entire memory array can therefore be read with a single fast_read command. when the highest address is reached, the address counter reverts to 000000h, allowing t he read sequence to continue indefinitely. the fast_read command is terminated by driving cs# high at any time during data output. the device rejects any fast_read command issued while it is executing a program, erase, or writ e registers operation, and continues the operation uninterrupted. figure 9.2 read data bytes at higher speed (fast_read) command sequence cs# sck si so command 24 bit address dummy byte hi-z data out 1 data out 2 msb msb 01 2 34 56 7 8 9 10 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 23 22 21 3 2 1 0 7 654 3 2 1 0 7 6 5 4 3 210 7 mode 3 mode 0
document number: 002-00648 rev. *j page 24 of 66 S25FL129P 9.3 dual output read mode (dor) the dual output read instruction is simila r to the fast_read instruction, except that the data is shifted out 2 bits at a time using 2 pins (si/io0 and so/io1) instead of 1 bit, at a maximum frequency of 80 mhz. the dual output read mode effectively doubles the data transfer rate compared to the fast_read instruction. the host system must first select the device by driving cs# low. the dual output read command is th en written to si, followed b y a 3-byte address (a23-a0) and a dummy byte. each bit is latched on the rising edge of sck. then the memory contents, at the address that is given, are shifted out two bits at a time through the io0 (si) and io1 (so) pins at a frequency f c on the falling edge of sck. the dual output read command sequence is shown in figure 9.3 and table 9.1 on page 21 . the first address byte specified can start at any location of the memory array. the device automatically increments to t he next higher address after each byte of da ta is output. the entire memory array can theref ore be read with a single dual output read command. when the highest address is reached, the address counter reverts to 00000h, allo wing the read sequence to continue indefinitely. it is important that the i/o pins be set to high-impeda nce prior to the falling edge of the first data out clock. the dual output read command is terminated by driving cs# high at any time during data output. the device rejects any dual output read command issued while it is executing a program, er ase, or write registers operatio n, and continues the operation uninterrupted. figure 9.3 dual output read instruction sequence cs# sck so/io1 si switches from input to output 24 bit address dummy byte hi-z byte 2 *msb 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 23 * 22 21 32107 * 6543210 6420 si/io0 012 34 56 7 8 9 10 instruction byte 1 7 5 31 7 * 5 31 7 * 6420 6
document number: 002-00648 rev. *j page 25 of 66 S25FL129P 9.4 quad output read mode (qor) the quad output read instruction is similar to the fast_read instru ction, except that the data is shifted out 4 bits at a time using 4 pins (si/io0, so/io1, w#/acc/io2 and hold#/ io3) instead of 1 bit, at a maximum frequency of 80 mhz. the quad output read mode effectively doubles the data transfer rate compared to the dual output read instruction, and is four times the data transf er rate of the fast_read instruction. the host system must first select the device by driving cs# low. the qu ad output read command is then written to si, followed b y a 3-byte address (a23-a0) and a dummy byte. each bit is latched on the rising edge of sck. then the memory contents, at the address that are given, are shif ted out four bits at a time through io0 (si), io1 (so), io2 (w#/acc), and io3 (hold#) pins at a frequency f c on the falling edge of sck. the quad output read command sequence is shown in figure 9.4 and table 9.1 on page 21 . the first address byte specified can start at any location of the memory array. the device automatically increments to t he next higher address after each byte of da ta is output. the entire memory array can theref ore be read with a single quad output read command. when the highest address is reached, the address counter reverts to 00000h, allo wing the read sequence to continue indefinitely. it is important that the i/o pins be set to high-impeda nce prior to the falling edge of the first data out clock. the quad output read command is terminated by driving cs# high at any time during data output. the device rejects any quad output read command issued while it is executing a program, er ase, or write registers operatio n, and continues the operation uninterrupted. the quad bit of configuration register must be set (cr bit1 = 1 ) to enable the quad mode capability of the s25fl device. figure 9.4 quad output read instruction sequence cs# sck si/io0 so/io1 w#/acc/io2 hold#/io3 si switches from input to output 24 bit address dummy byte hi-z *msb 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 23 * 22 21 321076543 2 * 10 4 012345678910 instruction 51 7 * 5 3 4 2 0 6 hi-z hi-z data out 1 data out 2 data out 3 data out 4 7 * 3 7 * 3 7 * 3 7 * 2 6 2 6 2 6 6 51 5151 4 0 4 0 4 0
document number: 002-00648 rev. *j page 26 of 66 S25FL129P 9.5 dual i/o high performa nce read mode (dior) the dual i/o high performance read instruction is similar to the d ual output read instruction, exc ept that it improves throughp ut by allowing input of the address bits (a23-a0) using two bits per sc k via two input pins (si/io2 and so/io1), at a maximum frequen cy of 80 mhz. the host system must first select the device by driving cs# low. the dual i/o high performance read command is then written to si, followed by a 3-byte address (a23-a0) and a 1-byte mode instru ction, with two bits latched on the rising edge of sck. then the memory contents, at the address that is given, are shift ed out two bits at a time through io0 (si) and io1 (so). the dual i/o high performance read command sequence is shown in figure 9.5 and table 9.1 on page 21 . the first address byte specified can start at any location of t he memory array. the device automatically in crements to the next higher address after e ach byte of data is output. the entire memory array can therefore be read with a single dual i/o high performance read command. when the highest address is reached, the address counter reverts to 00000h, allowing the read sequence to continue indefinitely . in addition, address jumps can be done without exiting the dual i/o high performance mode through the setting of the mode bits (after the address (a23-0) sequence, as shown in figure 9.5 ). this added feature removes t he need for the instruction sequence and greatly improves code execution (xip). the upper nibble (bits 7-4) of the mode bits control the length of the next dual i/o high performance instruction through the inclusion or exclusion of th e first byte instruction code. the lower nibble (bits 3-0) of t he mode bits are don?t care (?x?). if the mode bits equal axh, then t he device remains in dual i/o high performance read mode and the next address can be entered (after cs# is raised high and then asserted low) without requiring the bbh instruction opcode, as shown in figure 9.6 , thus eliminating eight cycles for the instruction sequence. however, if the mode bits are any value other than axh, then the next instruction (after cs# is raised high and then asserted low) requires the instruction sequence, which is nor mal operation. the following sequences will release the device from dual i/o high performance read mode; after which, the device ca n accept standard spi instructions: 1. during the dual i/o high performance inst ruction sequence, if the mode bits are any value other than axh, then the next time cs# is raised high and then asserted low, the device will be released from dual i/o high performance read mode. 2. furthermore, during any operation, if cs# toggles high to low to high for eight cycles (or less) and data input (io0 and io1) are not set for a valid instruction sequence, then the device will be released from dual i/o high performance read mode. it is important that the i/o pins be set to high-impeda nce prior to the falling edge of the first data out clock. the read instruction can be terminated by driving the cs# pin to the logic high state. the cs# pin can be driven high at any ti me during data output to terminate a read operation. figure 9.5 dual i/o high performance read instruction sequence cs# sck so/io1 io0 & io1 switches from input to output 24 bit address mode bits hi-z byte 2 *msb 28 29 30 31 18 19 20 21 22 23 24 25 26 27 23 * 22 21 3 2 1 0 7 * 6 5 4 si/io0 012345678910 instruction byte 1 7 * 7 * 6 20 7 * 3 1 5 3 1 5 3 1 2 0 6 4 2 0 6 4 2 0
document number: 002-00648 rev. *j page 27 of 66 S25FL129P figure 9.6 continuous dual i/o high performance read instruction sequence cs# sck so/io1 io0 & io1 switches from input to output 24 bit address mode bits byte 2 *msb 21 22 23 11 12 13 14 15 16 17 18 19 20 23 * 22 21 3 2 1 0 7 * 6 5 4 si/io0 01 910 byte 1 7 * 7 * 6 20 7 * 3 1 20 64 2 0 64 2 0 5 3 1 5 3 1
document number: 002-00648 rev. *j page 28 of 66 S25FL129P 9.6 quad i/o high performa nce read mode (qior) the quad i/o high performance read instruction is similar to the quad output read instruction, exc ept that it further improves throughput by allowing input of the address bits (a23-a0) using 4 bits per sck via four input pi ns (si/io0, so/io1, w#/acc/io2 and hold#/io3), at a maximum frequency of 80 mhz. the host system must first select the device by driving cs# low. the quad i/o high performance read command is then written to si, followed by a 3-byte address (a23-a0) and a 1-byte mode inst ruction, with four bits latched on the rising edge of sck. note that four dummy clocks are required prior to the da ta input. then the memory contents, at the address that is given, are shifted out four bits at a time through io0 (si), io1 (so), io2 (w#/acc), and io3 (hold#). the quad i/o high performance read command sequence is shown in figure 9.7 and table 9.1 on page 21 . the first address byte specified can start at any location of t he memory array. the device automatically in crements to the next higher address after e ach byte of data is output. the entire memory array can therefore be read with a single quad i/o high performance read command. when the highest address is reached, the address counter reverts to 00000h, allowing the read sequence to continue indefinitely . in addition, address jumps can be done wit hout exiting the quad i/o high performance mo de through the setting of the mode bits (after the address (a23-0) sequence, as shown in figure 9.7 ). this added feature the removes the need for the instruction sequence and greatly improves code execution (xip). the upper nibble (bits 7-4) of the mode bi ts control the length of the next quad i/o high performance instruction through the inclusion or exclusion of th e first byte instruction code. the lower nibble (bits 3-0) of t he mode bits are don't care (?x?). if the mode bi ts equal axh, then the device remains in q uad i/o high performance read mode and the next address can be entered (after cs# is raised high and then asserted low) without requiring the ebh instruction opcode, as shown in figure 9.8 , thus eliminating eight cycles for the instruction sequenc e. the following sequences will release the device from quad i/o high performance read mode; after which, the device can accept standard spi instructions: 1. during the quad i/o high performance instruction sequence, if the mode bits are any value other than axh, then the next time cs# is raised high and then asserted low the device will be released from quad i/o high performance read mode. 2. furthermore, during any operation, if cs# toggles high to low to high for eight cycles (or less) and data input (io0, io1, io2, and io3) are not set for a valid instruction sequen ce, then the device will be released from quad i/o high performance read mode. it is important that the i/o pins be set to high-impeda nce prior to the falling edge of the first data out clock. the read instruction can be terminated by driving the cs# pin to the logic high state. the cs# pin can be driven high at any ti me during data output to terminate a read operation. figure 9.7 quad i/o high performance instruction sequence cs# sck so/io1 io?s switches from input to output 24 bit address mode bits hi-z byte 2 *msb 23 24 25 26 13 14 15 16 17 18 19 20 21 22 23 * 19 2 1 0 6 5 4 si/io0 0123456789 instruction byte 1 7 * 6 7 * 3 5 3 1 2 0 4 dummy dummy hi-z hi-z w#/acc/io2 hold#/io3 22 18 21 17 20 16 7 * 3 7 * 3 6 2 6 2 5 1 5 1 4 0 4 0
document number: 002-00648 rev. *j page 29 of 66 S25FL129P figure 9.8 continuous quad i/o high performance instruction sequence 9.7 read identification (rdid) the read identification (rdid) command outputs the one-byte manufacturer identification, followed by the two-byte device identification and the bytes for the common flash interface (cfi) tables. the m anufacturer identification is assigned by jedec; for cypress devices, it is 01h. the device identification (2 bytes) and cfi bytes are assigned by the device manufacturer. see table 9.2 on page 30 for device id data. the common flash interface (cfi) specificat ion outlines device and host system software interrogation handshake, which allows vendor-specified software algorithms to be used for entire fam ilies of devices. software support can then be device-independent , jedec id-independent, and forward- and backward-compatible fo r the specified flash device families. flash vendors can standardize their existing inte rfaces for long-term comp atibility. the system ca n read cfi information at the addresses given i n table 9.3 . the host system must first select the device by driving cs# low. the rdid command is then written to si, and each bit is latche d on the rising edge of sck. one byte of manufa cture identification, two bytes of device id entification and sixt y-six bytes of exten ded device identification are then output from the memory array on so at a frequency f r , on the falling edge of sck. the maximum clock frequency for the rdid (9fh) command is 50 mhz (normal read). the manufacturer id and device id can be read repeatedly by applying multiples of six hundred and forty eight clock cycles. the manufacturer id, device id and cfi table can be continuousl y read as long as cs# is held low with a clock input. the rdid command sequence is shown in figure 9.9 and table 9.1 on page 21 . driving cs# high after the device identif ication data has been read at least once termi nates the rdid command. driving cs# high at any time during data output (for example, while reading the extended cfi bytes), also terminates the rdid operation. the device rejects any rdid command issued while it is executing a program, erase, or write regi sters operation, and continues the operation uninterrupted. *ms b cs# sck so/io1 io?s switches from input to output 24 bit address mode bits byte 2 13 14 15 16 23 * 19 2 1 0 6 5 4 si/io0 01 456789 byte 1 7 * 6 7 * 3 5 3 1 2 0 4 dummy dummy w#/acc/io2 hold#/io3 22 18 21 17 20 16 7 * 3 7 * 3 6 2 6 2 5 1 5 1 4 0 4 0 10 11 12
document number: 002-00648 rev. *j page 30 of 66 S25FL129P figure 9.9 read identification (rdid) command sequence and data-out sequence notes 1. byte 0 is manufacturer id of spansion. 2. byte 1 and 2 is device id. 3. byte 3 is extended device information string length, to i ndicate how many extended device information bytes will follow. 4. byte 4 indicates uniform 64 kb sector or uniform 256 kb sector device. 5. bytes 5 and 6 are spansion reserved (do not use). 6. for bytes 07h-0fh and 3dh-3fh, the data will be read as 0xff. 7. bytes 10h-50h are factory programmed per jedec standard. table 9.2 manufacturer and device id entification - rdid (9fh): device manufacturer identification device identification extended device identification byte 0 byte 1 byte 2 byte 3 byte 4 uniform 256 kb sector 01h 20h 18h 4dh 00h uniform 64 kb sector 01h 20h 18h 4dh 01h table 9.3 product group cfi quer y identification string byte data description 10h 11h 12h 51h 52h 59h query unique ascii string ?qry? 13h 14h 02h 00h primary oem command set 15h 16h 40h 00h address for primary extended table 17h 18h 00h 00h alternate oem command set (00h = none exists) 19h 1ah 00h 00h address for alternate oem extended table (00h = none exists) 646 13 210 9 8 7 6 5 4 0 31 30 29 28 instruction 1 645 652 34 33 32 655 654 653 sck si so high impedance extended device information cs# 0 1 2 20 21 22 23 24 25 26 644 647 manufacturer / device identification
document number: 002-00648 rev. *j page 31 of 66 S25FL129P table 9.4 product group cfi system interface string byte data description 1bh 27h v cc min. (erase/program): (d7-d4: volt, d3-d0: 100 mv) 1ch 36h v cc max. (erase/program): (d7-d4: volt, d3-d0: 100 mv) 1dh 00h v pp min. voltage (00h = no vpp pin present) 1eh 00h v pp max. voltage (00h = no vpp pin present) 1fh 0bh typical timeout per single byte program 2 n s 20h 0bh typical timeout for min. size page program 2 n s (00h = not supported) 21h 09h typical timeout per individual sector erase 2 n ms 22h 11h typical timeout for full chip erase 2 n ms (00h = not supported) 23h 01h max. timeout for byte program 2 n times typical 24h 01h max. timeout for page program 2 n times typical 25h 02h max. timeout per individual sector erase 2 n times typical 26h 01h max. timeout for full chip erase 2 n times typical (00h = not supported) table 9.5 product group cfi device geometry definition byte data description 27h 18h device size = 2 n byte; 28h 05h flash device interface description; 00h = x8 only 01h = x16 only 02h = x8/x16 capable 03h = x32 only 04h = single i/o spi, 3-byte address 05h = multi i/o spi, 3-byte address 29h 05h 2ah 08h max. number of bytes in multi-byte write = 2 n (00 = not supported) 2bh 00h 2ch 02h (uniform 64 kb sector) 01h (uniform 256 kb sector) number of erase block regions within device 1 = uniform device, 2 = parameter block 2dh 1fh (uniform 64 kb sector) 3fh (uniform 256 kb sector) erase block region 1 information (refer to cfi publication 100) 2eh 00h 2fh 10h (uniform 64 kb sector) 00h (uniform 256 kb sector) 30h 00h (uniform 64 kb sector) 04h (uniform 256 kb sector) 31h fdh (uniform 64 kb sector) 00h (uniform 256 kb sector) erase block region 2 information (refer to cfi publication 100) 32h 00h 33h 00h 34h 01h (uniform 64 kb sector) 00h (uniform 256 kb sector) 35h 00h erase block region 3 information (refer to cfi publication 100) 36h 00h 37h 00h 38h 00h 39h 00h erase block region 4 information (refer to cfi publication 100) 3ah 00h 3bh 00h 3ch 00h
document number: 002-00648 rev. *j page 32 of 66 S25FL129P note cfi data related to v cc and time-outs may differ from actual v cc and time-outs of the product. please consult the ordering information tables to obtain the v cc range for particular part numbers. please consult the ac characteristics on page 57 for typical timeout specifications. table 9.6 product group cfi primary v endor-specific extended query byte data description 40h 50h query-unique ascii string ?pri? 41h 52h 42h 49h 43h 31h major version number, ascii 44h 33h minor version number, ascii 45h 15h address sensitive unlock (bits 1-0) 00b = required, 01b = not required process technology (bits 5-2) 0000b = 0.23 m floating gate 0001b = 0.17 m floating gate 0010b = 0.23 m mirrorbit 0010b = 0.20 m mirrorbit 0011b = 0.11 m floating gate 0100b = 0.11 m mirrorbit 0101b = 0.09 m mirrorbit 1000b = 0.065 m mirrorbit 46h 00h erase suspend 0 = not supported, 1 = read only, 2 = read and write 47h 04h sector protect 00 = not supported, x = number of sectors in per smallest group 48h 00h temporary sector unprotect 00 = not supported, 01 = supported 49h 05h sector protect/unprotect scheme 04 = high voltage method 05 = software command locking method 08 = advanced sector protection method 4ah 00h simultaneous operation 00 = not supported, x = number of sectors outside bank 1 4bh 01h burst mode type 00 = not supported, 01 = supported 4ch 03h page mode type 00 = not supported, 01 = 4 word page, 02 = 8 word page, 03 = 256 byte page 4dh 85h acc (acceleration) supply minimum 00 = not supported, (d7-d4: volt, d3-d0: 100 mv) 4eh 95h acc (acceleration) supply maximum 00 = not supported, (d7-d4: volt, d3-d0: 100 mv) 4fh 07h w# protection 07 = uniform device with top or bottom write protect (user select) 50h 00h program suspend 00 = not supported, 01 = supported
document number: 002-00648 rev. *j page 33 of 66 S25FL129P 9.8 read-id (read_id) the read_id instruction provides the s25fl12 9p manufacturer and device information and is provided as an alternative to the release from deep power-down and read electronic signature (res), and the jedec read identification (rdid) commands. the instruction is initiated by driving the cs# pin low and shifti ng in (via the si input pin) the instruction code ?90h? follo wed by a 24- bit address (which is either 00000h or 00001h). following this, the manufacturer id and the device id are shifted out on the so output pin starting after the falling edge of the sck serial cl ock input signal. if the 24-bit address is set to 000000h, the m anufacturer id is read out first followed by the device id. if the 24-bit ad dress is set to 000001h, then the device id is read out first f ollowed by the manufacturer id. the manufacturer id and the device id are always shifted out on the so out put pin with the msb first, as shown in figure 9.10 . once the device is in read-id mode, the manufacturer id and device id output data toggles between address 000000h and 000001h until terminated by a low to high transition on the cs# input pin. the maximum clock frequency for the read - id (90h) command is at 104 mhz (fast_read). the manufacturer id and device id is output cont inuously until terminated by a low to high transition on cs# chip select input pin. figure 9.10 read-id (rdid) command timing diagram table 9.7 read_id data-out sequence address data manufacturer identification 00000h 01h device identification 00001h 17h cs# sck si so 0 high impedance 8 7 6 5 4 3 22 1931 30 28 10 9 45 44 43 42 41 40 39 38 37 36 35 34 33 32 47 46 23 22 21 0 1 2 3 0 1 2 3 4 5 6 7 instruction 24-bit address n o i t a c i f i t n e d i e c i v e d n o i t a c i f i t n e d i e r u t c a f u n a m b s m
document number: 002-00648 rev. *j page 34 of 66 S25FL129P 9.9 write enable (wren) the write enable (wren) command (see figure 9.11 ) sets the write enable latch (wel) bit to a 1, which enables the device to accept a write status register, program, or erase command. the wel bit must be set prior to every page program (pp), quad page program (qpp), parameter sector erase (p4e, p8e), eras e (se or be), write registers (wrr) and otp program (otpp) command. the host system must first drive cs# low, wr ite the wren command, and then drive cs# high. figure 9.11 write enable (wren) command sequence 9.10 write disable (wrdi) the write disable (wrdi) command (see figure 9.12 ) resets the write enable latch (wel) bi t to a 0, which disables the device from accepting a page program (pp), qu ad page program (qpp), parameter sector erase (p4e, p8e), erase (se, be), write registers (wrr) and otp program (otpp) co mmand. the host system must first drive cs# low, write the wrdi command, and then drive cs# high. any of following conditions resets the wel bit: ? power-up ? write disable (wrdi) command completion ? write registers (wrr) command completion ? page program (pp) command completion ? quad page program (qpp) completion ? parameter sector erase (p4e, p8 e) completion (applicable for the uniform 64 kb sector device only) ? sector erase (se) command completion ? bulk erase (be) command completion ? otp program (otpp) completion figure 9.12 write disable (wrdi) command sequence cs# sck si so hi-z command 012345 67 mode 3 mode 0 0 1 2 34 5 6 7 command cs# hi-z sck si so mode 3 mode 0
document number: 002-00648 rev. *j page 35 of 66 S25FL129P 9.11 read status register (rdsr) the read status register (rdsr) command out puts the state of the st atus register bits. table 9.8 shows the status register bits and their functions. the rdsr command may be written at any time, even while a program, erase, or write registers operation is in progress. the host system should check the write in progress (wip) bit before sending a new command to the device if an operation is already in progress. figure 9.13 shows the rdsr command sequence, which also shows that it is possible to read the status register continuously until cs# is driven high. the maximum clock frequency for the rdsr command is 104 mhz. figure 9.13 read status register (rdsr) command sequence the following describes the status and c ontrol bits of the status register. write in progress (wip) bit: indicates whether the device is bu sy performing a write registers, program, or erase operation. this bit is read-only, and is controlled internally by the device. if wip is 1, one of thes e operations is in progress; if wip is 0, no such operation is in progress. this bit is a read-only bit. write enable latch (wel) bit: determines whether the device will accept and execute a write register s, program, or erase command. when set to 1, the device accepts t hese commands; when set to 0, the device rejects the commands. this bit is set to 1 by writing the wren command, and set to 0 by the wrdi command, and is also automatically reset to 0 after the completion of a write registers, program, or eras e operation, and after a power down/power up se quence. wel cannot be di rectly set by the wrr command. block protect (bp2, bp1, bp0) bits: define the portion of the memory area that w ill be protected against any changes to the stored data. the block protection (bp2, bp1, bp0) bits are either volat ile or non-volatile, depending on the state of the non-volatile bit bpnv in the configuration register. the block protection (bp2 , bp1, bp0) bits are written wit h the write registers (wrr) table 9.8 S25FL129P status register bit status register bit bit function description 7 srwd status register write disable 1 = protects when w#/acc is low 0 = no protection, even when w#/acc is low 6 p_err programming error occurred 0 = no error 1 = error occurred 5 e_err erase error occurred 0 = no error 1 = error occurred 4 bp2 block protect protects selected blocks from program or erase 3 bp1 2 bp0 1 wel write enable latch 1 = device accepts write registers, program or erase commands 0 = ignores write registers, program or erase commands 0 wip write in progress 1 = device busy a write registers, program or erase operation is in progress 0 = ready. device is in standby mode and can accept commands. command hi-z msb msb status register out status register out 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 7 6 5 4 3 2 10 7 6 5 4 3 2 1 0 7 so si sck cs# mode 3 mode 0
document number: 002-00648 rev. *j page 36 of 66 S25FL129P instruction. when one or more of the block protect (bp2, bp1, bp0) bits is set to 1?s, the relevant memory area is protected ag ainst page program (pp), parameter sector eras e (p4e, p8e), sector erase (se), quad pa ge programming (qpp) and bulk erase (be) instructions. if the hardware protected mode is enabled, bp2:bp0 cannot be changed. the bulk erase (be) instruction can be executed only when the block protection (bp2, bp1, bp0) bits are set to 0?s. the default condition of the bp2-0 bits is binary 000 (all 0?s). erase error bit (e_err): the erase error bit is used as a erase operation su ccess and failure check. when the erase error bit is set to a ?1?, it indicates that there was an error which occurred in the last erase operation. with the erase error bit set to a ?1?, this bit is reset with the clear status register (clsr) command. program error bit (p_err): the program error bit is used as a program oper ation success and failure check. when the program error bit is set to a ?1?, it indicates that there was an erro r which occurred in the last program operation. with the program error bit set to a ?1?, this bit is reset with th e clear status register (clsr) command. status register write disable (srwd) bit: provides data protection when used togethe r with the write protect (w#/acc) signal. the status register write disable (srwd) bit is operated in conjunction with the write protect (w#/acc) input pin. the status register write disable (srwd) bit and the wr ite protect (w#/acc) signal allow the devi ce to be put in the hardware protected mode. with the status register write disable (srwd) bit set to a ?1? and the w#/a cc driven to the logic low state, the device e nters the hardware protected mode; the non-volatile bits of the stat us register (srwd, bp2, bp1, bp0) and the nonvolatile bits of the configuration register (tbparm, tbprot, bpnv and quad) becom e read-only bits and the write registers (wrr) instruction opcode is no longer accepted for execution. note that the p_err and e_err bits will not be set to a 1 if the application writes to a protected memory area. 9.12 read configuration register (rcr) the read configuration register (rcr) inst ruction opcode allows the configuration regi ster contents to be read out of the so serial output pin. the conf iguration register content s may be read at any time, even while a program, erase, or write cycle is in progress. when one of these cycles is in progress, it is recomm ended to the user to check the write in progress (wip) bit of th e status register before issuing a new inst ruction opcode to the device. the configurat ion register originally shows 00h when the device is first shipped from the factory to the customer. (refer to section 7.8 on page 11 , table 7.1 and table 7.1 on page 12 for more details.) figure 9.14 read configuration register (rcr) instruction sequence configuration register out n o i t c u r t s n i 13 0 1 29 8 7 6 5 4 0 14 13 12 11 15 1 32 0 7654 sck si so msb high impedance cs# configuration register out msb msb 1 32 0 7654 7 19 18 17 16 20 22 21 23
document number: 002-00648 rev. *j page 37 of 66 S25FL129P 9.13 write registers (wrr) the write registers (wrr) command allows changing the bits in the status and configuration re gisters. a write enable (wren) command, which itself sets the write enable latch (wel) in the status register, is r equired prior to writing the wrr command. table 9.8 shows the status register bits and their functions. the host system must drive cs# low, then write the wrr command and the appropriate data byte on si figure 9.15 . the wrr command cannot change the state of the write enable lat ch (bit 1). the wren command must be used for that purpose. the status register consists of one data byte in length; similarl y, the configuration register is also one data byte in length. the cs# pin must be driven to the logic low state during the entire duration of the sequence. the wrr command also controls the value of the status regi ster write disable (srwd) bit. the srwd bit and w#/acc pin together place the device in the hardware protected mode (h pm). the device ignores all wrr commands once it enters the hardware protected mode (hpm). table 9.9 shows that w#/acc must be driven low and the srwd bit must be 1 for this to occur. the write registers (wrr) instruction has no effect on the p/e e rror and the wip bits of the status and configuration registers . any bit reserved for the future is always read as a ?0? the cs# chip select input pin must be driven to the logic high state after the eighth (see figure 9.15 ) or sixteenth (see figure 9.16 ) bit of data has been latched in. if not, th e write registers (wrr) instru ction is not executed. if cs# is driven high after the eighth cycle then only the status register is wr itten to; otherwise, after the sixteenth cycle both the stat us and config uration regis ters are written to. as soon as the cs# chip select input pin is driven to t he logic high state, the self -timed write registers cycle is initiated. while the write registers cycle is in progress, the status regist er may still be read to check the value of the write in progre ss (wip) bit. the write in progress (wip) bit is a ?1? during the self-timed write registers cycle, and is a ?0? when it is completed. w hen the write registers cycle is completed, the wr ite enable latch (wel) is set to a ?0?. the wrr command can operate at a maximum clock frequency of 104 mhz. figure 9.15 write registers (wrr) instru ction sequence ? 8 data bits n i r e t s i g e r s u t a t s n o i t c u r t s n i 1 30 1 29 8 7 6 5 4 0 14 13 12 11 15 1 32 0 7654 sck si so msb high impedance cs#
document number: 002-00648 rev. *j page 38 of 66 S25FL129P figure 9.16 write registers (wrr) instruction sequence ? 16 data bits note as defined by the values in the block protect (bp2, bp1, bp0) bits of the status register, as shown in table 7.3 on page 13 . table 9.9 shows that neither w#/acc or srwd bit by themselves c an enable hpm. the device can enter hpm either by setting the srwd bit after driving w#/acc low, or by driving w#/acc low af ter setting the srwd bit. howeve r, the device disables hpm only when w#/acc is driven high. note that hpm only protects against changes to the status register. since bp2:bp0 c annot be changed in hpm, the size of the protected area of the memory array cannot be changed. note that hpm prov ides no protection to the memory array area outside tha t specified by bp2:bp0 (softw are protected mode, or spm). if w#/acc is permanently tied high, hpm can never be activated, and only the spm (block protect bi ts of the status register) ca n be used. the status and configuration registers origin ally default to 00h, when the device is first shipped from the factory to the cust omer. note: hpm is disabled when the quad i/o mode is enable d (quad bit = 1 in the co nfiguration register). w# becomes io2; therefore, hpm cannot be utilized. table 9.9 protection modes w#/ acc srwd bit mode write protection of registers memory content protected area unprotected area 11 software protected (spm) status and configuration registers are writable (if wren instruction has set the wel bit). the values in the srwd, bp2, bp1, and bp0 bits and those in the configuration register can be changed protected against page program, parameter sector erase, sector erase, and bulk erase ready to accept page program, parameter sector erase, and sector erase instructions 10 00 01 hardware protected (hpm) status and configuration registers are hardware write protected. the values in the srwd, bp2, bp1, and bp0 bits and those in the configuration register cannot be changed protected against page program, sector erase, and bulk erase ready to accept page program, sector erase instructions i i n s t r u c t i o n s t a t u s r e g i s t e r i n 1 3 2 1 0 9 8 7 6 5 4 0 1 4 1 3 1 2 1 1 1 5 1 3 2 0 7 6 5 4 s c k s i s o m s b h i g h i m p e d a n c e c s s # c o n f i g u r a t i o n r e g i s t e r i n 1 8 1 7 1 6 2 2 2 1 2 0 1 9 2 3 1 3 2 0 7 6 5 4 m s b
document number: 002-00648 rev. *j page 39 of 66 S25FL129P 9.14 page program (pp) the page program (pp) command changes specified bytes in the memory array (from 1 to 0 only ). a wren command is required prior to writing the pp command. the host system must drive cs# low, and then write the pp command, three address bytes, and at least one data byte on si. if th e 8 least significant address bits (a7-a0) are not all zero, all tr ansmitted data that goes beyond the end of the currently selec ted page are programmed from the starting address of the same page (from t he address whose 8 least significant bits are all zero). cs# m ust be driven low for the entire duration of the pp sequence. the command sequence is shown in figure 9.17 and table 9.1 on page 21 . the device programs only the last 256 data bytes sent to the de vice. if the 8 least significant address bits (a7-a0) are not al l zero, all transmitted data that goes beyond the end of the currently select ed page are programmed from the starting address of the same page (from the address whose 8 least signific ant bits are all zero). if fewer than 256 data bytes are sent to device, they are correctly programmed at the requested addresses without having an y effect on the other bytes in the same page. the host system must drive cs# high after the device has latched the 8th bi t of the data byte, other wise the device does not ex ecute the pp command. the pp operation begins as soon as cs# is driven high. the device inte rnally controls the timing of the operati on, which requires a period of t pp . the status register may be read to check the value of the write in progress (wip) bit while the pp operation is in progress. the wip bit is 1 during the pp operation, and is 0 when the operation is completed. the device intern ally resets the write enable latch to 0 before the operation completes (the exact timing is not specified). the device does not execute a page program (pp) command that specifies a page that is protected by the block protect bits (bp2:bp0) (see table 7.3 on page 13 ). figure 9.17 page program (pp) command sequence 0 34 33 32 31 30 29 28 10 9 8 7 6 5 4 3 2 1 35 36 37 38 39 46 45 44 43 42 41 40 47 48 49 50 51 52 53 54 55 2073 2072 2076 2075 2074 2079 2078 2077 23 22 21 3 21 07 6 5 43 2 1 0 data byte 1 24 bit address command data byte 2 data byte 3 data byte 256 msb msb msb msb msb sck si sck si 7 65 4 3 2 1 0 76 54 321 0 7 6 5 43210 cs# cs# mode 0 mode 3
document number: 002-00648 rev. *j page 40 of 66 S25FL129P 9.15 quad page program (qpp) the quad page program instruction is similar to the page pr ogram instruction, except that the quad page program (qpp) instruction allows up to 256 bytes of data to be programmed at previously erased (ffh) memory locations using four pins: io0 (s i), io1 (so), io2 (w#/acc), and io3 (hold#), instead of just one pin (si) as in the case of the page program (pp) instruction. this effectively increases the data transfer rate by up to four times, as compared to the page program (pp) instruction. the qpp fea ture can improve performance for prom programmer and applications that have slow clock speeds < 5 mhz. systems with faster clock speed will not realize much benefit for the qpp instruction since the inherent page program time is much greater than the time it take to clock-in the data. to use qpp, the quad enable bit in the co nfiguration register must be set (quad = 1). a write enable instruction must be executed before the device will accept the qu ad page program instruction (status register-1, wel = 1). the instruction is initi ated by driving the cs# pin low then shifting the instruction code ?3 2h? followed by a 24 bit address (a23-a0) and at least one data byte, into the io pins. the cs# pin must be held low for the entire length of the instruction while data is being sent to the device. all other functions of quad input page program ar e identical to standard page program. the qpp instruction sequence is shown below. figure 9.18 quad page program instruction sequence *msb cs# sck so/io1 instruction 24 bit address byte 2 39 23 * 5 si/io0 01 456789 byte 1 6 7 * 4 w#/acc/io2 hold#/io3 22 21 7 * 3 7 * 3 6 2 6 2 5 1 5 1 4 0 4 0 10 cs# sck so/io1 si/io0 w#/acc/io2 hold#/io3 2 3 28 29 32 33 34 35 36 37 38 30 31 byte 4 byte 3 3 2 1 0 5 6 7 * 4 3 2 1 0 3 2 1 0 51 40 41 44 45 46 47 48 49 50 42 43 54 55 52 53 536 537 538 539 540 541 542 543 byte 6 byte 5 byte 8 byte 7 byte 10 byte 9 byte 12 byte 11 byte 254 byte 253 byte 256 byte 255 7 * 3 6 2 5 1 4 0 7 * 3 6 2 5 1 4 0 7 * 3 6 2 5 1 4 0 7 * 3 6 2 5 1 4 0 7 * 3 6 2 5 1 4 0 7 * 3 6 2 5 1 4 0 7 * 3 6 2 5 1 4 0 7 * 3 6 2 5 1 4 0 7 * 3 6 2 5 1 4 0 7 * 3 6 2 5 1 4 0 7 * 3 6 2 5 1 4 0 7 * 3 6 2 5 1 4 0
document number: 002-00648 rev. *j page 41 of 66 S25FL129P 9.16 parameter sector erase (p4e, p8e) (only applicab le for the uniform 64 kb sector device) the parameter sector erase (p4e, p8e) command sets all bits at all addresses within a specified sector to a logic 1 (ffh). a wr en command is required prior to writing the parameter sector erase commands. the host system must drive cs# low, and th en write the p4e or p8e command, plus th ree address bytes on si. any address within the sector (see table 5.1 on page 8 ) is a valid address for the p4e or p8e command. cs# must be driven low for the entire duration of the p4e/p8e sequence. the command sequence is shown in figure 9.19 and table 9.1 on page 21 . the host system must drive cs# high after the device has latched the 24th bit of the p4e/p8e address, otherwise the device does not execute the command. the parameter sector erase operation be gins as soon as cs# is driven high. the device internally controls the timing of the operatio n, which requires a period of t se . the status register may be read to check the value of the write in progress (wip) bit while the parameter sector erase operatio n is in progress. the wip bit is 1 during the p4e/p8e operation, and is 0 when the operation is completed. the device internally rese ts the write enable latch to 0 before the operation completes ( the exact timing is not specified). a parameter sector erase (p4e, p8 e) instruction applied to a sector that has bee n write protected through the block protect bit s will not be executed. the parameter sector erase command (p8e) erases two of the 4 kb sectors in selected address space. the parameter sector erase command (p8e) erases two sequential 4 kb parameter se ctors in the selected address space. the address lsb is disregarded so that two sequential 4 kb parameter sectors are eras ed. the 24 bit address is any lo cation within the first sector to be erased (n), and the next sequential 4 kb parameter sector will also be erased (n+1 ). the 4 kb parameter sector will only be erased properly if n or n+1 is a valid 4 kb parameter sector. i. e. if n is not a valid 4k parameter sector, then it will not be erased. if n+1 is not a valid 4 kb parameter se ctor, then it will not be erased. note: the p4e and p8e commands do not apply to the uniform 256 kb sector device. figure 9.19 parameter sector erase (p4e , p8e) instruction sequence 1 30 1 29 8 7 6 5 4 0 31 30 29 28 instruction 24 bit address 23 21 22 1 32 0 sck si msb cs# 20h or 40h
document number: 002-00648 rev. *j page 42 of 66 S25FL129P 9.17 sector erase (se) the sector erase (se) command sets all bits at all addresses with in a specified sector to a logic 1. a wren command is required prior to writing the se command. the host system must drive cs# low, and then write the se command plus three address bytes on si. any address within the sector (see table 7.3 on page 13 ) is a valid address for the se command. cs# must be driven low for the entire duration of the se sequence. the command sequence is shown in figure 9.20 and table 9.1 on page 21 . the host system must drive cs# high after the device has latched the 24th bit of the se address, otherwise the device does not execute the command. the se operation begins as soon as cs# is driven high. the device internally controls the timing of the operation, which requires a period of t se . the status register may be read to check the value of the write in progress (wip) bit while the se operation is in progress. the wip bit is 1 during the se operation, and is 0 when the operation is completed. the device internally resets the write enable latch to 0 before the operation completes (the ex act timing is not specified). the device only executes a se command for those sectors which are not protected by the block protect bits (bp2:bp0) (see table 7.3 on page 13 ). otherwise, the dev ice ignores the command. a 64 kb sector erase (d8h) command issued on 4 kb or 8 kb erase sectors will erase all sectors in the specified 64 kb region. however, please note that a 4 kb sector erase (20h) or 8 kb sector erase (40h) command will not work on a 64 kb sector. figure 9.20 sector erase (se) command sequence cs# sck si so msb command 24 bit address 01 2 3 4 5 6 7 8 9 10 28 29 30 31 23 22 21 3 2 1 0 hi-z mode 0 mode 3
document number: 002-00648 rev. *j page 43 of 66 S25FL129P 9.18 bulk erase (be) the bulk erase (be) command sets all the bi ts within the entire memory array to logic 1s. a wren command is required prior to writing the be command. the host system must drive cs# low, and then write the be command on si. cs# must be driven low for the entire duration of the be sequence. the command sequence is shown in figure 9.21 and table 9.1 on page 21 . the host system must drive cs# high after the device has latche d the 8th bit of the ce command , otherwise the device does not execute the command. the be operation begins as soon as cs# is driven high. the device internally controls the timing of the operation, which requires a period of t be . the status register may be read to check the value of the write in progress (wip) bit while the be operation is in progress. the wip bit is 1 during the be operation, and is 0 when the operation is completed. the device internally resets the write enable latch to 0 before the operation completes (the ex act timing is not specified). the device only executes a be command if al l block protect bits (bp2:bp0) are 0 (see table 7.3 on page 13 ). otherwise, the device ignores the command. figure 9.21 bulk erase (be) command sequence 01 2 4 56 7 command cs# sck si 3 so hi-z mode 0 mode 3
document number: 002-00648 rev. *j page 44 of 66 S25FL129P 9.19 deep power-down (dp) the deep power-down (dp) command provides the lowest power c onsumption mode of the device. it is intended for periods when the device is not in active use, and ig nores all commands except for the release from deep power-down (res) command. the dp mode therefore provides the maximum data protection against unintended write operations. the standard standby mode, which the device goes into automatically when cs# is high (and all operat ions in progress are complete), should generally be used for the lowest power consumption when the quickest return to device activity is required. the host system must drive cs# low, and th en write the dp command on si. cs# must be driven low for the entire duration of the dp sequence. the command sequence is shown in figure 9.22 and table 9.1 on page 21 . the host system must drive cs# high after the device has latche d the 8th bit of the dp command , otherwise the device does not execute the command. after a delay of t dp, the device enters the dp mode and current reduces from i sb to i dp (see table 16.1 on page 55 ). once the device has entered the dp mode, all commands are ignored except the res command (which releases the device from the dp mode). the res command also provides the electronic si gnature of the device to be output on so, if desired (see section 9.20 and 9.20.1 ) . dp mode automatically terminates when power is removed, and the device always powers up in the standard standby mode. the device rejects any dp command i ssued while it is executing a program, erase, or write registers operat ion, and continues the operation uninterrupted. figure 9.22 deep power-down (dp) command sequence cs# sck si so standby mode deep power-down mode command 0 1 234 56 7 t dp hi-z mode 0 mode 3
document number: 002-00648 rev. *j page 45 of 66 S25FL129P 9.20 release from deep power-down (res) the device requires the release from deep power-down (res) comm and to exit the deep power-down mode. when the device is in the deep power-down mode, all commands except res are ignored. the host system must drive cs# low and wr ite the res command to si. cs# must be driven low for the entire duration of the sequence. the command sequence is shown in figure 9.23 and table 9.1 on page 21 . the host system must drive cs# high t res(max) after the 8-bit res command byte. the de vice transitions from dp mode to the standby mode after a delay of t res (see figure 18.1 ). in the standby mode, the device ca n execute any read or write command. note: the res command dose not reset the write enable latch (wel) bit. figure 9.23 release from deep power-down (res) command sequence cs# sck si so 0 1 23 4 5 6 7 command deep power-down mode t res standby mode mode 0 hi-z mode 3
document number: 002-00648 rev. *j page 46 of 66 S25FL129P 9.20.1 release from deep power-down and read electronic signature (res) the device features an 8-bit electronic signature, which can be read using the res command. see figure 9.24 and table 9.1 on page 21 for the command sequence and signature value. the electronic signature is not to be conf used with the identification data obtained using the rdid command. the device offers the elec tronic signature so that it ca n be used with previous devices t hat offered it; however, the electronic signature should not be used for new designs, which shou ld read the rdid data instead. after the host system drives cs# low, it mu st write the res command follow ed by 3 dummy bytes to si (each bit is latched on si during the rising edge of sck). the electronic signature is then output on so; each bit is shifted out on the falling edge of s ck. the res operation is terminated by driving cs# high after the electron ic signature is read at least once. additional clock cycles o n sck with cs# low cause the device to outpu t the electronic si gnature repeatedly. when cs# is driven high, the device transitions fr om dp mode to the standby mode after a delay of t res , as previously described. the res command always provides access to the electronic signatu re of the device and can be appl ied even if dp mode has not been entered. any res command issued while an erase, program, or write regi sters operation is in progress no t executed, and the operation continues uninterrupted. note: the res command does not reset the write enable latch (wel) bit. figure 9.24 release from deep power-down and res command sequence 9.21 clear status register (clsr) the clear status register command resets bit sr5 (erase fail flag ) and bit sr6 (program fail flag). it is not necessary to set the wel bit before the clear sr fail flags command is executed. th e wel bit will be unchanged afte r this command is executed. figure 9.25 clear status register (clsr) instruction sequence cs# sck si so 3 dummy bytes hi-z msb deep power-down mode standby mode 0 1 2 34567 8 9 10 28 29 30 31 32 33 34 35 36 37 38 electronic id command t res 23 22 21 3 2 10 7 65 4 32 1 0 msb 39 3 2 7 6 5 4 0 i n s t r u c t i o n s c k s i 1 c s s #
document number: 002-00648 rev. *j page 47 of 66 S25FL129P 9.22 otp program (otpp) the otp program command programs data in the otp region, which is in a different address space from the main array data. refer to otp regions on page 48 for details on the otp region. the protocol of t he otp program command is the same as the page program command, except that the otp progr am command requires exactly one byte of data; otherwise, the command will be ignored. to program the otp in bit gr anularity, the rest of the bits with in the data byte can be set to ?1?. the otp memory space can be programmed one or more times, pr ovided that the otp memory sp ace is not locked (as described in ?locking otp regions?). subsequent otp programming can be performed only on the unprogram med bits (that is, ?1? data). note: the write enable (wren) command must precede t he otpp command before programming of the otp can occur. figure 9.26 otp program instruction sequence 9.23 read otp data bytes (otpr) the read otp data bytes command reads data from the otp region. refer to ? otp regions ? for details on the otp region. the protocol of the read otp data bytes command is the same as the fast read data bytes command except that it will not wrap to the starting address after the otp address is at it s maximum; instead, the data will be indeterminate. figure 9.27 read otp instruction sequence 1 3 2 1 0 9 8 7 6 5 4 0 3 1 3 0 2 9 2 8 i n s t r u c t i o n 2 4 b i t a d d r e s s 2 3 2 1 2 2 1 3 2 0 3 6 3 5 3 4 3 3 3 2 3 9 3 8 3 7 1 3 2 0 7 6 5 4 d a t a b y t e 1 s c k s i m s b m s b c s# 1 30 1 29 8 7 6 5 41 3 030 29 28 instruction 24 bit address 23 21 22 1 32 0 1 32 0 7654 36 35 34 33 9 3 2 338 37 1 32 0 7654 dummy byte 44 43 42 41 7 4 0 446 45 data out 1 data out 2 sck si so msb high impedance 7 msb cs
document number: 002-00648 rev. *j page 48 of 66 S25FL129P 10. otp regions the otp regions are separately addressable from the main array and consists of two 8-byte (esn), thirty 16-byte, and one 10-byt e regions that can be individually locked. ? the two 8-byte esn region is a special order part (please co ntact your local cypress sales representative for further details). the two 8-byte regions enable permanent part ident ification through an electronic serial number (esn). the customer can utilize the esn to pair a flash device with the system cpu/asic to prevent system cloning. the cypress factory programs and locks the lower 8-byte esn with a 64-bit randomly generated, unique number. the upper 8-byte esn is left blank for customer use or, if special ordered, cypress can program (and lock) in a unique customer id. ? the thirty 16-byte and one 10-byte otp regions are open for the customer usage. ? the thirty 16-byte, one 10-byte, and upper 8-byte esn otp regions can be individually locked by the end user. once locked, the data cannot changed. the locki ng process is permanent and cannot be undone. the following general conditions should be noted with respect to the otp regions: ? on power-up, or following a hardware reset, or at the end of an otpp or an otpr command, the device reverts to sending commands to the normal address space. ? reads or programs outside of the otp regions will be ignored ? the otp region is not accessible when the device is exec uting an embedded program or embedded erase algorithm. ? the acc function is not available when accessing the otp regions. ? the thirty 16-byte and one 10-byte otp regions are left open for customer usage, but special care of the otp locking must be maintained, or else a malevolent user can permanently lock the otp regions. this is not a concern, if the otp regions are not used. 10.1 programming otp address space the protocol of the otp program command (42h) is the same as the page program command. refer to table 9.1 for the command description and protocol. the otp program command can be issued multiple times to any given otp address, but this address space can never be erased. after a given otp region is programme d, it can be locked to prevent further programming with the otp lock registers (refer to section 10.3 ). the valid address range for otp program is depicted in the figure below. otp program operations outside the valid otp address range will be ignored. 10.2 reading otp data the protocol of the otp read command (4bh) is the sa me as that of the fast read command. refer to table 9.1 for the command description and protocol. the valid address range for otp reads is depicted in the figure below. otp read operations outside th e valid otp address range will yield indeterminate data. 10.3 locking otp regions in order to permanently lock the esn and otp regions, individual bi ts at the specified addresses can be set to 1 to lock specif ic regions of otp memory, as highlighted in figures 10.1 and 10.2 . lock register esn1 (bit 0) lock register esn2 (bit 1) esn1 region contains esn2 region contains standard part 1h 1h 0h 0h special order part 1h 1h/0h unique random pattern factory/customer programmed pattern
document number: 002-00648 rev. *j page 49 of 66 S25FL129P figure 10.1 otp memory map - part 1 notes 1. bit 0 at address 0x100h locks esn1 region. 2. bit 1 at address 0x100h locks esn2 region. 3. bits 2-7 (?x?) are not programmable and will be ignored. address otp region 0x213h 0x204h 0x203h 0x1f4h 0x1f3h 0x1e4h 0x1e3 0x1d4h 0x1d3h 0x1c4h 0x1c3h 0x1b4h 0x1b3h 0x1a4h 0x1a3h 0x194h 0x193h 0x184h 0x183h 0x174h 0x173h 0x164h 0x163h 0x154h 0x153h 0x144h address bit locks region? 0x143h 0otp1 1otp2 0x134h 2otp3 0x133h 3otp4 4otp5 0x124h 5otp6 0x123h 6otp7 7otp8 0x114h 0otp9 0x113h 1otp10 0x112h 2otp11 0x111h 3otp12 4otp13 0x10ah 5otp14 0x109h 6otp15 7otp16 0x102h 0esn1 0x101h reserved 1esn2 0x100h 2 - 7 r eserved 16 bytes (ot p15) 16 bytes (ot p14) 16 bytes (ot p13) 16 bytes (ot p12) 16 bytes (ot p5) 16 bytes (ot p11) 16 bytes (ot p10) 16 bytes (ot p9) 16 bytes (ot p6) 16 bytes (ot p7) 16 bytes (ot p8) 0x100h 0x112h 0x113h 16 bytes (ot p16) 8 bytes (es n1) 8 bytes (es n2) 16 bytes (ot p1) 16 bytes (ot p2) 16 bytes (ot p3) 16 bytes (ot p4) x x x x x x bit 1 bit 0 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0
document number: 002-00648 rev. *j page 50 of 66 S25FL129P figure 10.2 otp memory map - part 2 note 1. bit 7 (?x?) at address 0x215h is not programmable and will be ignored. address otp region 0x2ffh 0x2f6h 0x2f5h 0x2e6h 0x2e5 0x2d6h 0x2d5h 0x2c6h 0x2c5h 0x2b6h 0x2b5h 0x2a6h 0x2a5h 0x296h 0x295h 0x286h 0x285h 0x276h 0x275h 0x266h 0x265h address b it locks region? 0otp17 0x256h 1otp18 0x255h 2otp19 3otp20 0x246h 4otp21 0x245h 5otp22 6otp23 0x236h 7otp24 0x235h 0otp25 1otp26 0x226h 2otp27 0x225h 3otp28 4otp29 0x216h 5otp30 0x215h 6 otp31 0x214h 7 reserved 16 bytes (ot p21) 0x214h 0x215h 16 bytes (ot p17) 16 bytes (ot p18) 16 bytes (ot p19) 16 bytes (ot p20) 16 bytes (ot p27) 16 bytes (ot p26) 16 bytes (ot p25) 16 bytes (ot p22) 16 bytes (ot p23) 16 bytes (ot p24) 10 bytes (ot p31) 16 bytes (ot p30) 16 bytes (ot p29) 16 bytes (ot p28) bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 x bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0
document number: 002-00648 rev. *j page 51 of 66 S25FL129P 11. power-up and power-down during power-up and power-down, certain conditions must be observed. cs# must follow the voltage applied on v cc , and must not be driven low to select the device until v cc reaches the allowable values as follows (see figure 11.1 and table 11.1 on page 52 ): ? at power-up, v cc (min.) plus a period of t pu ? at power-down, gnd a pull-up resistor on chip select (cs#) typically meets proper power-up and power-down requirements. no read, write registers, program, or erase command should be sent to the device until v cc rises to the v cc min., plus a delay of t pu . at power-up, the device is in standby mode (not deep power-down mode) and the wel bit is reset (0). each device in the host system should have the v cc rail decoupled by a suitable capacitor cl ose to the package pins (this capacitor is generally of the order of 0.1 f), as a precaution to stabilizing the v cc feed. when v cc drops from the operating voltage to below the minimum v cc threshold at power-down, all operations are disabled and the device does not respond to any commands. no te that data corruption may result if a power-down occurs while a write registers, program, or erase operation is in progress. figure 11.1 power-up timing diagram v cc v cc (max) v cc (min) full device access t pu time
document number: 002-00648 rev. *j page 52 of 66 S25FL129P figure 11.2 power-down and voltage drop 12. initial delivery state the device is delivered with the memory arra y erased i.e. all bits are set to 1 (ffh ) upon initial factory shipment. the status register and configuration register contains 00h (all bits are set to 0). the lock register (address 0x100h) is written to 0x01 and es n1 (addresses 0x102h-0x109h) are wr itten with a 64-bit randomly generated, unique number (taken from section 10. on page 48 ). 13. program acceleration via w#/acc pin the program acceleration function requires applying v hh to the w#/acc input, and then waiting a period of t wc . minimum t vhh rise and fall times is required for w#/acc to change to v hh from v il or v ih . removing v hh from the w#/acc pin returns the device to normal operation after a period of t wc . table 11.1 power-up / power-down voltage and timing symbol parameter min max unit v cc(min) v cc (minimum operation voltage) 2.7 v v cc (cut-off) v cc (cut off where re-initialization is needed) 2.4 v v cc (low) v cc (low voltage for initialization to occur at read/standby) v cc (low voltage for initialization to occur at embedded) 0.2 2.3 v t pu v cc (min.) to device operation 300 s t pd v cc (low duration time) 1.0 s no device access allowed device access allowed time v cc t pu t pd v cc (max) v cc (min) v cc (cut-off) v cc (low)
document number: 002-00648 rev. *j page 53 of 66 S25FL129P figure 13.1 acc program acceleration timing requirements note only read status register (rdsr) and page program (pp) operation are allow when acc is at (v hh ). the w#/acc pin is disabled during quad i/o mode. table 13.1 acc program acceleration specifications symbol parameter min. max unit v hh a cc pin voltage high 8.5 9.5 v t vhh a cc voltage rise and fall time 2.2 s t wc acc at v hh and v il or v ih to first command 5 s acc command ok v hh v il or v ih t vhh t wc t wc t vhh v il or v ih
document number: 002-00648 rev. *j page 54 of 66 S25FL129P 14. electrical specifications 14.1 absolute maximum ratings note 1. minimum dc voltage on input or i/os is - 0.5v. during voltage transitions, inputs or i/os may undershoot gnd to - 2.0v for periods of up to 20 ns. see figure 14.1 . maximum dc voltage on input or i/os is v cc + 0.5v. during voltage transitions inputs or i/os may overshoot to v cc + 2.0v for periods up to 20 ns. see figure 14.2 . 2. no more than one output may be shorted to ground at a time. duration of the short circuit should not be greater than one seco nd. 3. stresses above those listed under ?absolute maximum ratings? may cause permanent damage to the device. this is a stress ratin g only; functional operation of the device at these or any other conditions abov e those indicated in the operational sections of this data sheet is not implied. ex posure of the device to absolute maximum rating conditions for extended periods may affect device reliability. figure 14.1 maximum negative overshoot waveform figure 14.2 maximum positive overshoot waveform 15. operating ranges note operating ranges define those limits between wh ich functionality of the device is guaranteed. description rating ambient storage temperature -65c to +150c voltage with respect to ground: all inputs and i/os -0.5v to v cc +0.5v output short circuit current (2) 200 ma table 15.1 operating ranges description rating ambient operating temperature (t a ) industrial ?40c to +85c automotive in-cabin ?40c to +105c positive power supply voltage range 2.7v to 3.6v 20 ns 20 ns +0.8v ?0.5v 20 ns ?2.0v 20 ns 20 ns v cc +2.0v v cc +0.5v 20 ns 2.0v
document number: 002-00648 rev. *j page 55 of 66 S25FL129P 16. dc characteristics this section summarizes the dc characteristics of the device. de signers should check that the operating conditions in their cir cuit match the measurement conditions specif ied in the test specifications in table 17.1 on page 56 , when relying on the quoted parameters. table 16.1 dc characteristics (cmos compatible) symbol parameter test conditions limits unit min. typ * max v cc supply voltage 2.7 3.6 v v hh acc program acceleration voltage v cc = 2.7v to 3.6v 8.5 9.5 v v il input low voltage -0.3 0.3 x v cc v v ih input high voltage 0.7 x v cc v cc +0.5 v v ol output low voltage i ol = 1.6 ma, v cc = v cc min. 0.4 v v oh output high voltage i oh = -0.1 ma v cc -0.6 v i li input leakage current v cc = v cc max, v in = v cc or gnd ? 2a i lo output leakage current v cc = v cc max, v in = v cc or gnd ? 2a i cc1 active power supply current - read (so = open) at 80 mhz (dual or quad) 38 ma at 104 mhz (serial) 25 at 40 mhz (serial) 12 i cc2 active power supply current (page program) cs# = v cc 26 ma i cc3 active power supply current (wrr) cs# = v cc 15 ma i cc4 active power supply current (se) cs# = v cc 26 ma i cc5 active power supply current (be) cs# = v cc 26 ma i sb1 standby current (industrial temperature range parts) cs# = v cc ; so + v in = gnd or v cc 80 200 a standby current (automotive in-cabin temperature range parts) 80 250 a i pd deep power-down current cs# = v cc ; so + v in = gnd or v cc 310 a *typical values are at t ai = 25c and v cc = 3v
document number: 002-00648 rev. *j page 56 of 66 S25FL129P 17. test conditions figure 17.1 ac measurements i/o waveform table 17.1 test specifications symbol parameter min max unit c l load capacitance 30 pf input rise and fall times 5 ns input pulse voltage 0.2 v cc to 0.8 v cc v input timing reference voltage 0.3 v cc to 0.7 v cc v output timing reference voltage 0.5 v cc v 0.8 v cc 0.2 v cc 0.7 v cc 0.3 v cc input levels input and output timing reference levels 0.5 v cc
document number: 002-00648 rev. *j page 57 of 66 S25FL129P 18. ac characteristics notes 1. typical program and erase times assume the following conditions: 25 c, vcc = 3.0v; 10,000 cycles; checkerboard data pattern. 2. under worst-case conditions of 85c; v cc = 2.7v; 100,000 cycles. 3. acceleration mode (9v acc) only in program mode, not erase. 4. only applicable as a constraint for wrr instruction when srwd is set to a ?1?. figure 18.1 ac characteristics symbol (notes) parameter (notes) min. (notes) typ (notes) max (notes) unit f r sck clock frequency for read command dc 40 mhz sck clock frequency for rdid command dc 50 mhz f c sck clock frequency for all others: fast_read, pp, qpp, p4e, p8e, se, be, dp, res, wren, wrdi, rdsr, wrr, read_id dc 104 (serial) 80 (dual/quad) mhz t wh , t ch (5) clock high time 4.5 ns t wl , t cl (5) clock low time 4.5 ns t crt , t clch clock rise time (slew rate) 0.1 v/ns t cft , t chcl clock fall time (slew rate) 0.1 v/ns t cs cs# high time (read instructions) cs# high time (program/erase) 10 50 ns t css cs# active setup time (relative to sck) 3 ns t csh cs# active hold time (relative to sck) 3 ns t su:dat data in setup time 3 ns t hd:dat data in hold time 2 ns t v clock low to output valid 0 8 (serial) ? 9.5 (dual/quad) ? 6.5 (serial) ? 8 (dual/quad) ? 7 (dual/quad) ? ns t ho output hold time 2 ns t dis output disable time 8ns t hlch hold# active setup time (relative to sck) 3 ns t chhh hold# active hold time (relative to sck) 3 ns t hhch hold# non active setup time (relative to sck) 3 ns t chhl hold# non active hold time (relative to sck) 3 ns t hz hold# enable to output invalid 8 ns t lz hold# disable to output valid 8 ns t wps w#/acc setup time (4) 20 ns t wph w#/acc hold time (4) 100 ns t w wrr cycle time 50 ms t pp page programming (1)(2) 1.5 3 ms t ep page programming (acc = 9v) (1)(2)(3) 1.2 2.4 ms t se sector erase time (64 kb) (1)(2) 0.5 2 sec sector erase time (256 kb) (1)(2) 2 8 sec t pe parameter sector erase time (4 kb or 8 kb) (1)(2) 200 800 ms t be bulk erase time (1)(2) 128 256 sec t res deep power-down to standby mode 30 s t dp time to enter deep power-down mode 10 s t vhh acc voltage rise and fall time 2.2 s t wc acc at vhh and vil or vih to first command 5 s
document number: 002-00648 rev. *j page 58 of 66 S25FL129P 5. t wh + t wl must be less than or equal to 1/f c . 6. ? full vcc range (2.7 ? 3.6v) and cl = 30 pf 7. ? regulated vcc range (3.0 ? 3.6v) and cl = 30 pf 8. ? regulated vcc range (3.0 ? 3.6v) and cl = 15 pf 18.1 capacitance figure 18.2 spi mode 0 (0,0) input timing figure 18.3 spi mode 0 (0,0) output timing symbol parameter test conditions min typ max unit c in input capacitance (applies to sck, po7-po0, si, cs#) v out = 0v 9.0 12.0 pf c out output capacitance (applies to po7-po0, so) v in = 0v 12.0 16.0 pf cs# sck si so t csh t css t csh t css t crt t cft msb in lsb in hi-z t su:dat t hd:dat t cs cs# sck so lsb out t wh t wl t dis t v t ho t v t ho
document number: 002-00648 rev. *j page 59 of 66 S25FL129P figure 18.4 hold# timing figure 18.5 write protect setup and hold timing during wrr when srwd = 1 t chhl t hz t chhh t hlch t hhch t lz cs# sck so si hold# w# cs# sck si so hi-z t wps t wph
document number: 002-00648 rev. *j page 60 of 66 S25FL129P 19. physical dimensions 19.1 so3 016 ? 16-pin wide plastic smal l outline package (300- mil body width)
document number: 002-00648 rev. *j page 61 of 66 S25FL129P 19.2 wson 8-contact (6 x 8 mm) no-lead package (wnf008) g1015 \ 16-038.30 \ 07.21.11 notes: 1. dimensioning and tolerancing conforms to asme y14.5m - 1994. 2. all dimensions are in millmeters. 3. n is the total number of terminals. 4 dimension ?b? applies to metallized terminal and is measured between 0.15 and 0.30mm from terminal tip. if the terminal has the optional radius on the other end of the terminal, the dimension ?b? should nt be measured in that radius area. 5 nd refer to the number of terminals on d side. 6. max. package warpage is 0.05mm. 7. maximum allowable burrs is 0.076mm in all directions. 8 pin #1 id on top will be laser marked. 9 bilateral coplanarity zone applies to the exposed heat sink slug as well as the terminals. 10 a maximum 0.15mm pull back (l1) may be present. symbol min nom max note e 1.27 bsc. n 8 3 nd 4 5 l 0.45 0.50 0.55 b 0.35 0.40 0.45 4 d2 4.70 4.80 4.90 e2 5.70 5.80 5.90 d 6.00 bsc e 8.00 bsc a 0.70 0.75 0.80 a1 0.00 0.02 0.05 k 0.20 min. l1 0.00 --- 0.15 10 package wnf008
document number: 002-00648 rev. *j page 62 of 66 S25FL129P 19.3 fab024 ? 24-ball ball gr id array (6 x 8 mm) package
document number: 002-00648 rev. *j page 63 of 66 S25FL129P 19.4 fac024 ? 24-ball ball gr id array (6 x 8 mm) package package fac024 jedec n/a d x e 8.00 mm x 6.00 mm nom package symbol min nom max note a --- --- 1.20 profile a1 0.25 --- --- ball height a2 0.70 --- 0.90 body thickness d 8.00 bsc. body size e 6.00 bsc. body size d1 5.00 bsc. matrix footprint e1 3.00 bsc. matrix footprint md 6 matrix size d direction me 4 matrix size e direction n 24 ball count ? b 0.35 0.40 0.45 ball diameter e 1.00 bsc. ball pitchl sd/ se 0.5/0.5 solder ball placement depopulated solder balls j package outline type 3642 f16-038.9 \ 09.10.09 notes: 1. dimensioning and tolerancing methods per asme y14.5m-1994. 2. all dimensions are in millimeters. 3. ball position designation per jep95, section 4.3, spp-010. 4. e represents the solder ball grid pitch. 5. symbol "md" is the ball matrix size in the "d" direction. symbol "me" is the ball matrix size in the "e" direction. n is the number of populated solder ball positions for matrix size md x me. 6 dimension "b" is measured at the maximum ball diameter in a plane parallel to datum c. datum c is the seating plane and is defined by the crowns of the solder balls. 7 sd and se are measured with respect to datums a and b and define the position of the center solder ball in the outer row. when there is an odd number of solder balls in the outer row sd or se = 0.000. when there is an even number of solder balls in the outer row, sd or se = e/2 8. "+" indicates the theoretical center of depopulated balls. 9 a1 corner to be identified by chamfer, laser or ink mark, metallized mark indentation or other means. 10 outline and dimensions per customer requirement.
document number: 002-00648 rev. *j page 64 of 66 S25FL129P 20. revision history spansion publication number: S25FL129P_00_09 document history page document title: S25FL129P, 128-mbit 3.0 v flash memory document number: 002-00648 rev. ecn no. orig. of change submission date description of change ** ? ? may 26, 2009 initial release. *a ? ? june 22, 2009 quad page programming: corrected description. configuration register: removed the no te in the bottom of the page. added suggested cross setting table. data protection modes: corrected descr iption for software protected mode. accelerated programming operation: added note. read identification (rdid)corrected description. added statement for operating clock frequency. corrected figure. read status register (rdsr): added statement for operating clock frequency. read configuration register (rcr): added reference section. write registers (wrr): added note for hardware protect mode. removed all occurrences of quad operations. parameter sector erase (p4e, p8e): corrected description. added note. sector erase (se): corrected description. release from deep power-down (res): added note. release from deep power-down and read electronic signature (res): added note. otp regions: corrected description for esn. added esn table. initial delivery state: added description for the rock register. ac characteristics: corrected description of note. physical dimensions: added bga package. *b ? ? october 14, 2009 global: changed datasheet de signation from advanced information to prelim- inary changed all references to rdid clock rate from 40 to 50 mhz connection diagrams: added note rega rding exposed central pad on bottom of package to the wson connection diagram. added ?5 x 5 pin configuration? to figure 2.3 title. added 6 x 4 pi n configuration bga connection diagram ordering information: added 20, 21, 30, and 31 model numbers for bga pack- ages. added automotive in-cabin temp erature ordering opt ion. added low- halogen material option valid combinations: changed valid bga model number combinations to 20, 21, 30, and 31. changed valid bga material option to low-halogen. added automotive in-cabin temperature valid combinations for all packages. added note 2 regarding contact factory for availability of automotive in-cabin temper- ature grade parts physical dimensions: added fac024 bga package dc characteristics: added note 1 indicating that icsb1 maximum value only applies to industrial temperature grade parts ac characteristics: added min and max values for sector erase time (256 kb) *c ? ? november 2, 2009 ordering information: removed note 2 dc characteristics: added separate standby current values for industrial and automotive in-cabin temperature range parts. removed note 1.
document number: 002-00648 rev. *j page 65 of 66 S25FL129P *d ? ? august 12, 2010 global: the data sheet went fr om a ?preliminary? designation to full production. sector address table: in table 8.2, corrected the end address of ss30 from 01e000h to 01efffh. command definitions: in table 9.1, corrected the qior one byte command code from 1110 1111 to 1110 1011. read identification: in table 9.5 added cfi data of bytes 2dh to 34h for the 256 kb sector products. sector erase: clarified that the device only execut es a se command for those sectors which are not protected by the block protect bits. operating ranges: added the automotive in-cabin range. *e ? ? october 1, 2010 configuration register: clar ified that tbparm and tbprot must be selected at the initial configuration of the de vice, before any program or erase opera- tions. command definitions: in the instruction set table, corrected the clsr data byte cycle value from 1 to 0. sector erase (se): clarified that a 64 kb sector erase command will work on 4 kb and 8 kb sectors. clear status register: removed incomple te statement regarding internal state machine. otp regions: clarified that for locking otp regions, setting the bit refers to changing the value from 0 to 1. *f ? ? may 16, 2012 added text for recommending fl128s as migration device. *g ? ? september 21, 2012 ac characteristics: changed output hold time (tho) to 2 ns (min). physical dimensions: updated the package outline drawing for so3016 and wson 6x8 packages. *h ? ? january 30, 2013 capacitance: added ?typical? values column. corrected ?max? values for cin / cout (input / output capacitance) *i 4925992 bwha september 18, 2015 updated to cypress template *j 5967710 aesatmp8 november 15, 2017 updated logo and copyright. document history page (continued) document title: S25FL129P, 128-mbit 3.0 v flash memory document number: 002-00648 rev. ecn no. orig. of change submission date description of change
document number: 002-00648 rev. *j revised november 15, 2017 page 66 of 66 ? cypress semiconductor corporation, 2009-2017. this document is the property of cypress semiconductor corporation and its subs idiaries, including spansion llc (?cypress?). this document, including any software or firmware included or referenced in this document (?software?), is owned by cypress under the intellec tual property laws and treaties of the united states and other countries worldwide. cypress reserves all rights under such laws and treaties and does not, except as specifically stated in this paragra ph, grant any license under its patents, copyrights, trademarks, or other intellectual property rights. if the software is not accompanied by a license agreement and you do not otherwise have a writte n agreement with cypress governing the use of the software, then cypress hereby grants you a personal, non-exclusive, nontransferable license (without the right to sublicense) (1) under its copyright rights in the software (a) for software provided in source code form, to modify and reproduce the software solely for use with cypress hardware products, only internally within your organization, and (b) to distribute the software in binary code form externally to end users (either directly or indirectly through resellers and distributors), solely for use on cypress hardware product units, and (2) u nder those claims of cypress's patents that are infringed by the software (as provided by cypress, unmodified) to make, use, distribute, and import the software solely for use with cypress hardware product s. any other use, reproduction, modification, translation, or compilation of the software is prohibited. to the extent permitted by applicable law, cypress makes no warranty of any kind, express or implied, with regard to this docum ent or any software or accompanying hardware, including, but not limited to, the implied warranties of merchantability and fitness for a particular purpose. to the extent permitted by applicable law, cypress reserves the right to make changes to this document without further notice. cypress does n ot assume any liability arising out of the application or use of any product or circuit described in this document. any information provided in this document, including any sample design informati on or programming code, is provided only for reference purposes. it is the responsibility of the user of this document to properly design, program, and test the functionality and safety of any appli cation made of this information and any resulting product. cypress products are not designed, intended, or authorized fo r use as critical components in systems de signed or intended for the operation of w eapons, weapons systems, nuclear inst allations, life-support devices or systems, other medical devices or systems (including resuscitation equipment and surgical implants), pollution control or hazar dous substances management, or other uses where the failure of the device or system could cause personal injury, death, or property damage (?unintended uses?). a critical component is any compon ent of a device or system whose failure to perform can be reasonably expected to cause the failure of the device or system, or to affe ct its safety or effectiveness. cypress is not liable, in whol e or in part, and you shall and hereby do release cypress from any claim, damage, or other liability arising from or related to all uninte nded uses of cypress products. you shall indemnify and hold cyp ress harmless from and against all claims, costs, damages, and other liabilities, including claims for personal inju ry or death, arising from or related to any unintended uses of cypress products. cypress, the cypress logo, spansion, the spansion logo, and combinations thereof, wiced, psoc, capsense, ez-usb, f-ram, and tra veo are trademarks or registered trademarks of cypress in the united states and other countries. for a more complete list of cypress trademarks, visit cypress.com. other names and brand s may be claimed as property of their respective owners. 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